A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.