公开(公告)号：US06171909B2

公开(公告)日：2001-01-09

申请号：US09293434

申请日：1999-04-16

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.

Abstract translation: 描述了一种用于形成闪存单元的堆叠栅极的方法。 第一电介质层，导电层和氮化硅层依次形成在衬底上。 在氮化硅层上形成光刻胶图形。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻氮化硅层，导电层，第一介电层和衬底，直到在衬底中形成多个沟槽。 在衬底上形成绝缘层，其中绝缘层在导电层的顶表面和导电层的底表面之间具有表面水平。 导电间隔物形成在导电层和氮化硅层的侧壁上，其中导电间隔物和导电层用作第一栅极导电层。 去除氮化硅层。 第二电介质层和第二栅极导电层形成在衬底上。 将第二栅极导电层，第二介电层和第一栅极导电层图案化以分别形成控制栅极，图案化电介质层和浮置栅极。

公开(公告)号：US06214667B1

公开(公告)日：2001-04-10

申请号：US09292870

申请日：1999-04-16

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L21336

CPC classification number: H01L27/11519 ,  H01L27/115 ,  H01L27/11521

Abstract: An improved method for fabricating a flash memory on a semiconductor substrate is provided. A patterned gate oxide layer and a patterned mask layer are formed on the substrate. Hard material spacers are formed on sidewalls of the gate oxide layer and the mask layer. A shallow trench isolation is formed in the substrate using the mask layer and the hard material spacers as masks. The hard material spacers and the mask layer are removed. A tunneling oxide layer is formed on a portion of the substrate beside the gate oxide layer. A floating gate is formed over the gate oxide layer and the tunneling oxide layer. A dielectric layer is formed over the floating gate. A control gate is formed over the dielectric layer.

Abstract translation: 提供了一种用于在半导体衬底上制造闪速存储器的改进方法。 在衬底上形成图案化的栅极氧化物层和图案化的掩模层。 硬质材料间隔物形成在栅极氧化物层和掩模层的侧壁上。 使用掩模层和硬质材料间隔物作为掩模在衬底中形成浅沟槽隔离。 去除硬质材料间隔物和掩模层。 在栅极氧化物层旁边的衬底的一部分上形成隧道氧化物层。 在栅极氧化物层和隧道氧化物层上形成浮栅。 在浮栅上方形成介电层。 在电介质层上形成控制栅极。

公开(公告)号：US06294812B1

公开(公告)日：2001-09-25

申请号：US09306119

申请日：1999-05-06

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract translation: 闪存单元。 在控制门的侧壁上形成间隔物。 因此，可以通过形成间隔物来形成自对准的源极/漏极区域。 隧道氧化层然后形成在源/漏区而不是在控制栅上。 因此，隧道氧化物层由自对准工艺形成。

公开(公告)号：US6153472A

公开(公告)日：2000-11-28

申请号：US241544

申请日：1999-02-01

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for fabricating a flash memory is provided. The method contains sequentially forming a tunneling oxide layer, a polysilicon layer, and a silicon nitride layer on a semiconductor substrate. Patterning the silicon nitride layer, polysilicon layer, the tunneling oxide layer, and the substrate forms a trench in the substrate. A shallow trench isolation (STI) structure is formed to fill the trench up the silicon nitride layer. The silicon nitride layer is removed to expose the polysilicon layer and a portion of each sidewall of the STI structure. A polysilicon spacer is formed on each exposed sidewall of the STI structure. An upper portion of the STI structure is removed so as to expose a portion of each sidewall of the polysilicon layer. The polysilicon layer serves as a floating gate. A conformal dielectric layer and a top polysilicon layer are formed over the substrate. The top polysilicon layer, the dielectric layer, and the polysilicon layer are patterned to form a strip control gate, which covers the floating gate, that is a remaining portion of the polysilicon layer on the tunneling oxide layer.

Abstract translation: 提供一种制造闪存的方法。 该方法包括在半导体衬底上依次形成隧道氧化物层，多晶硅层和氮化硅层。 对氮化硅层，多晶硅层，隧道氧化物层和衬底进行图案化，在衬底中形成沟槽。 形成浅沟槽隔离（STI）结构以填充氮化硅层的沟槽。 去除氮化硅层以暴露多晶硅层和STI结构的每个侧壁的一部分。 在STI结构的每个暴露的侧壁上形成多晶硅间隔物。 去除STI结构的上部，以暴露多晶硅层的每个侧壁的一部分。 多晶硅层用作浮栅。 在衬底上方形成保形电介质层和顶部多晶硅层。 图案化顶部多晶硅层，电介质层和多晶硅层以形成带状控制栅极，该栅极控制栅极覆盖浮动栅极，该浮栅是隧道氧化物层上的多晶硅层的剩余部分。

公开(公告)号：US6114204A

公开(公告)日：2000-09-05

申请号：US306348

申请日：1999-05-06

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11521

Abstract: A method of fabricating a flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract translation: 一种制造闪存单元的方法。 在控制门的侧壁上形成间隔物。 因此，可以通过形成间隔物来形成自对准的源极/漏极区域。 隧道氧化层然后形成在源/漏区而不是在控制栅上。 因此，隧道氧化物层由自对准工艺形成。

公开(公告)号：US6048768A

公开(公告)日：2000-04-11

申请号：US267760

申请日：1999-03-11

Applicant: Yen-Lin Ding ,  Gary Hong

Inventor： Yen-Lin Ding ,  Gary Hong

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method for manufacturing a flash memory. A substrate having a patterned pad oxide layer formed thereon and a patterned mask layer on the pad oxide layer is provided. A doped region is formed in the substrate exposed by the patterned mask layer and the pad oxide layer. A spacer is formed on the sidewall of the patterned mask layer and the pad oxide layer to cover a portion of the doped region. A trench is formed in the substrate exposed by the mask layer and the spacer. An insulating layer is formed to fill the trench, wherein the insulating layer leveled with a top surface of the patterned mask layer. The patterned mask layer and the spacer are removed to respectively expose the patterned oxide layer and the portion of the doped region. A self-aligned tunnel oxide layer is formed on the portion of the doped region. A patterned first conductive layer is formed over the substrate to expose portions of the patterned pad oxide layer above the substrate excluding the doped region. A self-aligned doped region is formed in the substrate under the patterned pad oxide layer exposed by the patterned first conductive layer. A dielectric layer is formed on the patterned first conductive layer and the self-aligned doped region. A patterned second conductive layer is formed over the substrate.

Abstract translation: 一种用于制造闪速存储器的方法。 提供其上形成有图案化的衬垫氧化物层的衬底和衬垫氧化物层上的图案化掩模层。 在由图案化掩模层和衬垫氧化物层暴露的衬底中形成掺杂区域。 在图案化掩模层的侧壁和衬垫氧化物层上形成间隔物以覆盖掺杂区域的一部分。 在由掩模层和间隔物暴露的衬底中形成沟槽。 形成绝缘层以填充沟槽，其中绝缘层与图案化掩模层的顶表面平齐。 去除图案化的掩模层和间隔物以分别暴露图案化氧化物层和掺杂区域的部分。 在掺杂区域的部分上形成自对准的隧道氧化物层。 图案化的第一导电层形成在衬底上，以暴露除了掺杂区域之外的衬底上的图案化衬垫氧化物层的部分。 在由图案化的第一导电层暴露的图案化的衬垫氧化物层下面的衬底中形成自对准掺杂区域。 在图案化的第一导电层和自对准掺杂区上形成介电层。 在衬底上形成图案化的第二导电层。

公开(公告)号：US6143603A

公开(公告)日：2000-11-07

申请号：US286021

申请日：1999-04-05

Applicant: Yen-Lin Ding

Inventor： Yen-Lin Ding

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method for manufacturing a dual-cylinder bottom electrode. Because the node contact hole is formed by self-aligned etching and the materials of the spacers are conductive materials, the node contact hole is smaller than the resolution of the photolithography. Hence, the size of the device can be greatly reduced. Furthermore, because of the dual-cylinder bottom electrode, the surface area of the bottom electrode is enlarged in a limited space. Therefore, the capacitance of the capacitor is increased.

Abstract translation: 一种制造双缸底电极的方法。 由于节点接触孔是通过自对准蚀刻形成的，并且间隔物的材料是导电材料，所以节点接触孔小于光刻的分辨率。 因此，可以大大减少装置的尺寸。 此外，由于双筒底部电极，底部电极的表面积在有限的空间内扩大。 因此，电容器的电容增加。

公开(公告)号：US6001686A

公开(公告)日：1999-12-14

申请号：US89245

申请日：1998-06-02

Applicant: Yen-Lin Ding

Inventor： Yen-Lin Ding

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

Abstract: A method of fabricating a capacitor on a bit line of a DRAM. A substrate having a gate, a bit line, a source/drain region and an insulating layer covering the gate and the bit line is provided. A first conductive layer and an oxide layer are formed successively on the insulating layer. The oxide layer and the first conductive layer are defined to form a contact hole to expose the source/drain region. An insulating spacer is formed on the sidewall of the contact hole, and the first conductive layer and the second conductive layer are defined so they may be used as a lower electrode. A dielectric layer is formed on the first conductive layer and the second conductive layer. A third conductive layer as an upper electrode of a capacitor is formed on the dielectric layer.

Abstract translation: 一种在DRAM的位线上制造电容器的方法。 提供了具有栅极，位线，源极/漏极区域和覆盖栅极和位线的绝缘层的衬底。 在绝缘层上依次形成第一导电层和氧化物层。 限定氧化物层和第一导电层以形成接触孔以暴露源极/漏极区域。 绝缘垫片形成在接触孔的侧壁上，第一导电层和第二导电层被定义为可以用作下电极。 在第一导电层和第二导电层上形成介电层。 在电介质层上形成作为电容器的上电极的第三导电层。

公开(公告)号：US06306720B1

公开(公告)日：2001-10-23

申请号：US09492563

申请日：2000-01-27

Applicant: Yen-Lin Ding

Inventor： Yen-Lin Ding

IPC: H01L2120

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: A method of forming a capacitor of a mixed-mode device is described. Trenches used for forming a trench-type capacitor are simultaneously formed in a provided substrate while forming a shallow trench isolation. A conductive region used as a lower electrode is formed by ion implantation. A gate oxide layer, used for dielectric film, and a polysilicon layer, used as a gate and an upper electrode, are formed over the substrate and over the trenches. A trench-type capacitor is thus formed.

Abstract translation: 描述了形成混合模式装置的电容器的方法。 用于形成沟槽型电容器的沟槽在形成浅沟槽隔离的同时在所提供的衬底中同时形成。 通过离子注入形成用作下电极的导电区域。 用于电介质膜的栅极氧化物层和用作栅极和上部电极的多晶硅层形成在衬底上并在沟槽之上。 由此形成沟槽型电容器。