A method for implementing shallow trench isolation by using a non-critical chemical mechanical polishing method in an integrated circuit. After STI regions are etched and insulator oxide layer is deposited and etched back, a planarized insulator oxide layer is formed. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Thereafter, a non-critical CMP process is used to polish the cap layer on the smaller active regions, then the insulator oxide layer under cap layer is removed by wet etch. Subsequently, a wet etch is used to remove the cap layer and silicon nitride layer. Finally, the shallow trench isolation process is completed after the pad oxide is removed.