发明授权
US06184753B2 Clock delay circuitry producing clock delays less than the shortest delay element
失效
时钟延迟电路产生小于最短延迟元件的时钟延迟
- 专利标题: Clock delay circuitry producing clock delays less than the shortest delay element
- 专利标题(中): 时钟延迟电路产生小于最短延迟元件的时钟延迟
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申请号: US09082474申请日: 1998-05-21
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公开(公告)号: US06184753B2公开(公告)日: 2001-02-06
- 发明人: Kouichi Ishimi , Kazuyuki Ishikawa
- 申请人: Kouichi Ishimi , Kazuyuki Ishikawa
- 优先权: JP9-345621 19971215
- 主分类号: H03K5159
- IPC分类号: H03K5159
摘要:
A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.