公开(公告)号：US06614865B1

公开(公告)日：2003-09-02

申请号：US09476127

申请日：2000-01-03

申请人： Kouichi Ishimi

发明人： Kouichi Ishimi

IPC分类号： H03D324

CPC分类号： H03L7/16 ,  G06F1/08 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/095

摘要： A clock generator includes a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; and a phase adjusting circuit for adjusting a phase of an internal clock signal with that of an external clock signal. The frequency divider further includes a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a lock signal supplied from the phase adjusting circuit is active. The frequency divider generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is made inactive. The period of the particular clock signal is preferably set at a value greater than a phase adjustable range of the internal clock signal by the phase adjusting circuit, and particularly at a value equal to the longest period of the divided clock signals generated by the frequency divider. This makes it possible to prevent frequency shift involved in frequency switching in a conventional clock generator, and to save power.

摘要翻译： 时钟发生器包括：分频器，用于通过根据分频比控制信号划分输入时钟信号来输出分频时钟信号; 以及用于调整内部时钟信号与外部时钟信号的相位相位的相位调整电路。 只要从相位调整电路提供的锁定信号有效，分频器进一步包括用于禁止分频比控制信号的分频比控制信号禁止电路。 只要分频比控制信号被禁止，分频器产生特定的时钟信号，并且当锁定信号无效时，通过使分频比控制信号与特定时钟信号同步来改变分频时钟信号的频率。 特定时钟信号的周期优选地通过相位调整电路被设置为大于内部时钟信号的相位可调范围的值，特别是等于由分频器产生的分频时钟信号的最长周期的值 。 这使得可以防止常规时钟发生器中的频率切换中涉及的频移，并且节省功率。

公开(公告)号：US06366150B1

公开(公告)日：2002-04-02

申请号：US09666118

申请日：2000-09-20

申请人： Kouichi Ishimi

发明人： Kouichi Ishimi

IPC分类号： H03H1126

CPC分类号： H03K5/00006 ,  G06F1/08 ,  H03K5/133 ,  H04L7/0331 ,  H04L7/0337

摘要： In a multiplying circuit for providing a pulsed output clock signal having a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.

摘要翻译： 在用于提供具有脉冲输入时钟信号的倍数的频率的脉冲输出时钟信号的乘法电路中，当输入外部复位信号时，通过初始化计数器来初始化数字延迟线的延迟， 来自时钟发生器的输出时钟信号的脉冲小于预定的乘法器。 将数字延迟线的延迟设置为紧接着初始化之后的最小值，然后逐渐增加以便输出所需的输出时钟信号。

公开(公告)号：US06225840B1

公开(公告)日：2001-05-01

申请号：US09387896

申请日：1999-09-01

申请人： Kouichi Ishimi

发明人： Kouichi Ishimi

IPC分类号： H03B1900

CPC分类号： G06F1/04 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/095 ,  H03L7/0997 ,  H03L7/113

摘要： When a reset signal (PLL-RST) is input, an arithmetic unit (12) measures the cycle of an input clock (IN) with a pulse counter (9) and based on the measured cycle, calculates a count value such that a delay clock (DL-OUT) and an input clock (IN) may come into synchronization with each other, to set it to a counter (13). The counter (13) thereafter changes the count value step by step in accordance with an output signal from a phase comparator (18). After the count value of the counter (13) is set by the arithmetic unit (12), an arithmetic unit (30) calculates a count value such that an output clock (PLL-OUT) and the input clock (IN) may come into synchronization with each other, to set it to a counter (31). The counter (31) changes the count value step by step in accordance with an output signal from a phase comparator (35) only when the two phases compared by the phase comparator (18) coincide with each other. With this configuration, a transition period to achieve a stable output clock can be reduced.

摘要翻译： 当输入复位信号（PLL-RST）时，运算单元（12）利用脉冲计数器（9）测量输入时钟（IN）的周期，并且基于所测量的周期，计算计数值，使得延迟 时钟（DL-OUT）和输入时钟（IN）可以彼此同步，将其设置为计数器（13）。 然后，计数器（13）根据来自相位比较器（18）的输出信号逐步地改变计数值。 在计算器（13）的计数值由算术单元（12）设定后，算术单元（30）计算出输出时钟（PLL-OUT）和输入时钟（IN）可以进入的计数值 彼此同步，将其设置为计数器（31）。 只有当相位比较器（18）相比较的两相相互一致时，计数器（31）才能根据来自相位比较器（35）的输出信号逐步地改变计数值。 利用这种配置，可以减少实现稳定输出时钟的过渡期。

公开(公告)号：US6049238A

公开(公告)日：2000-04-11

申请号：US178580

申请日：1998-10-26

申请人： Kazuyoshi Shimizu ,  Kouichi Ishimi ,  Katsunori Sawai

发明人： Kazuyoshi Shimizu ,  Kouichi Ishimi ,  Katsunori Sawai

IPC分类号： H03K3/027 ,  H03K3/86 ,  H03L7/06 ,  H03L7/08 ,  H03L7/181

CPC分类号： H03K3/027 ,  H03K3/86 ,  H03L7/06 ,  H03L7/08 ,  H03L7/181

摘要： A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock. This can reduce the phase difference between the input clock and the phase-locked clock, and hence to solve a problem of a conventional clock generator in that a delay time of a digital delay line in a phase lock circuit must be lengthened with a reduction in the multiplication number of the frequency multiplied clock, which requires a greater number of delay elements because of a large occupying area of the delay elements and a decoder, thereby increasing the circuit scale and cost of a chip to reduce the multiplication number of the frequency multiplied clock.

摘要翻译： 包括倍频器，锁相电路和分频器的时钟发生器。 倍频器通过乘以输入时钟的频率来产生倍频时钟。 锁相电路检测输入时钟和分频时钟之间的相位差，并通过将倍频时钟延迟与相位差对应的量来产生锁相时钟，其锁相与输入时钟相锁相。 分频器在每个固定周期内检测锁相时钟的特定脉冲，并通过相对于锁相时钟的特定脉冲对相位锁定时钟进行分频来产生分频时钟。 特别地，分频器检测紧接在输入时钟下降沿之前的特定脉冲。 这可以减小输入时钟和锁相时钟之间的相位差，因此解决传统的时钟发生器的问题在于，锁相电路中的数字延迟线的延迟时间必须延长，同时减少 频率倍增时钟的倍数，由于延迟元件的占用面积大，解码器需要较大数量的延迟元件，从而增加了芯片的电路规模和成本，从而减少倍频的倍数 时钟。

公开(公告)号：US06466073B1

公开(公告)日：2002-10-15

申请号：US09670584

申请日：2000-09-27

申请人： Yoshio Yukinari ,  Kouichi Ishimi

发明人： Yoshio Yukinari ,  Kouichi Ishimi

IPC分类号： G06F108

CPC分类号： G06F1/08 ,  H03L7/16

摘要： Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequency-divided clocks such that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency, is slightly delayed against all of the other generated frequency-divided clocks. When changing the frequency of an output clock, a multiplexer switches from a previously selected one of the plurality of generated frequency-divided clocks to a desired clock in responsive to a control signal. The desired frequency-divided clock is then furnished as the output clock. Even when the plurality of frequency-divided clocks are not in phase with each other because of unit-to-unit variation when manufacturing the frequency dividing circuit, or due to changes in the operating conditions such as ambient temperature and voltages, the first clock pulse generated when the multiplexer performs the switching operation cannot have a shorter pulse width than pulses of the frequency-divided clock having the highest frequency.

摘要翻译： 时钟发生电路包括一个分频电路，用于将输入时钟的频率除以彼此不同的多个预定分频比，以产生多个分频时钟，使得分频时钟由 最小分频比，即具有最高频率的分频时钟，对所有其它产生的分频时钟稍微延迟。 当改变输出时钟的频率时，响应于控制信号，多路复用器从多个生成的分频时钟中的先前选择的一个切换到期望的时钟。 然后将期望的分频时钟作为输出时钟。 即使当制造分频电路时由于单位变化而导致多个分频时钟彼此不相位，或者由于诸如环境温度和电压的操作条件的变化，第一时钟脉冲 当多路复用器执行切换操作时产生的脉冲宽度不能比具有最高频率的分频时钟的脉冲具有更短的脉冲宽度。

公开(公告)号：US06259293B1

公开(公告)日：2001-07-10

申请号：US09413528

申请日：1999-10-06

申请人： Kiyoshi Hayase ,  Kouichi Ishimi

发明人： Kiyoshi Hayase ,  Kouichi Ishimi

IPC分类号： H03H1126

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00032 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995

摘要： Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock. The delay circuitry further includes a register for storing information to set a certain time delay, and a delay unit including a plurality of delay elements each of which provides an input with a time delay that is controlled by the control signal from the PLL, for determining the number of delay elements through which an input signal is to be passed according to the information stored in the register, so as to provide the input signal with the predetermined time delay.

摘要翻译： 延迟电路包括锁相环或PLL，用于将施加到其上的参考时钟的相位与要比较的另一个时钟的相位相比较，以产生具有对应于参考时钟和其它相位的相位之间的相位差的值的控制信号 时钟，用于使用连接到一个环路中的至少多个延迟元件产生另一个时钟，由所述多个延迟元件中的每一个提供的时间延迟由所述控制信号控制，并且用于改变所述控制信号的值，使得 另一个时钟与参考时钟同相。 所述延迟电路还包括用于存储用于设定一定时间延迟的信息的寄存器，以及包括多个延迟元件的延迟单元，每个延迟元件为由输入端提供来自PLL的控制信号控制的时间延迟输入，以确定 根据存储在寄存器中的信息通过其输入输入信号的延迟元件的数量，以便为输入信号提供预定的时间延迟。

公开(公告)号：US06714087B2

公开(公告)日：2004-03-30

申请号：US10122233

申请日：2002-04-16

申请人： Tomohiro Sakurai ,  Kouichi Ishimi

发明人： Tomohiro Sakurai ,  Kouichi Ishimi

IPC分类号： H03B2700

CPC分类号： H03L7/0995 ,  H03K3/0315

摘要： A current mirror circuit consisting of two P-channel MOS transistors in an operating current control section controls an operating current of a ring oscillator circuit in accordance with a current value of a constant current flowing in the current mirror circuit. A control voltage input section and a first current mirror resistance section in the operating current control section control the current value of the constant current generated by the current mirror circuit in accordance with a control voltage, and changes a range in which the constant current value is changed in response to a change of the control voltage, in accordance with a control signal.

摘要翻译： 由工作电流控制部分中的两个P沟道MOS晶体管组成的电流镜电路根据在电流镜电路中流动的恒定电流的电流值来控制环形振荡器电路的工作电流。 工作电流控制部中的控制电压输入部和第一电流镜电阻部根据控制电压来控制由电流镜电路产生的恒定电流的电流值，并且使恒定电流值为 响应于控制电压的变化，根据控制信号而改变。

公开(公告)号：US06184753B2

公开(公告)日：2001-02-06

申请号：US09082474

申请日：1998-05-21

申请人： Kouichi Ishimi ,  Kazuyuki Ishikawa

发明人： Kouichi Ishimi ,  Kazuyuki Ishikawa

IPC分类号： H03K5159

CPC分类号： H03K5/135 ,  G06F1/04 ,  G06F1/10

摘要： A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

摘要翻译： 振荡电路具有用于产生延迟时钟信号的时钟延迟电路的延迟环。 时钟延迟电路具有选择器并且具有多个具有彼此不同的延迟时间的延迟元件。 时钟延迟电路可以产生小于任何单个延迟元件的延迟时间的时滞，该时间延迟基于不同延迟元件的时间延迟之间的差异。 相位比较器将与延迟环相关联的信号的相位与参考时钟信号的相位相比较，产生相位差时钟信号。 延迟设定电路可以使选择器根据来自相位比较器的相位差信号以减少相位差的方式改变一个延迟时钟信号的选择。

公开(公告)号：US5708803A

公开(公告)日：1998-01-13

申请号：US689115

申请日：1996-07-30

申请人： Kouichi Ishimi ,  Yuichi Saito

发明人： Kouichi Ishimi ,  Yuichi Saito

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/00

CPC分类号： G06F9/383 ,  G06F12/0802

摘要： A data processor, with high processing performance in many fields of application, having a selector 41 which enables a cache memory of direct map system to be selectively used as a built-in cache memory or a built-in RAM in order to realize a data processor which can perform high-speed processing by decreasing the number of abortions of the processing as much as possible when branch is predicted in the pipeline processing mechanism, and an FB register 61B which holds an address to be accessed so that cache memory or external storage (main storage 28) may be accessed when branch is not predicted in the pipeline processing mechanism and only a cache memory may be accessed but accessing to the main storage 28 may be prohibited when branch is predicted, wherein the main storage 28 can be accessed by the address held in the FB register 61B at the moment it becomes accessible.

摘要翻译： 在许多应用领域中具有高处理性能的数据处理器具有选择器41，其使直接地图系统的高速缓冲存储器能够选择性地用作内置高速缓冲存储器或内置RAM，以实现数据 处理器，其可以通过在流水线处理机构中预测分支时尽可能多地减少处理的流失次数来执行高速处理;以及FB寄存器61B，其保存要访问的地址，使得高速缓存或外部存储 （主存储器28）可以在流水线处理机构中未预测到分支时被访问，并且只有高速缓冲存储器可以被访问，但是当预测分支时可能禁止访问主存储器28，其中主存储器28可以被 在FB寄存器61B中保持的地址变为可访问的地址。

公开(公告)号：US06771100B2

公开(公告)日：2004-08-03

申请号：US10166267

申请日：2002-06-11

申请人： Kouichi Ishimi

发明人： Kouichi Ishimi

IPC分类号： H03L700

CPC分类号： G06F1/04

摘要： A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.

摘要翻译： 时钟信号从时钟振荡器提供给门电路。 在复位信号为“H”电平的期间，将时钟信号提供给内部电路。 当复位信号变为“L”电平时，由门控制电路执行控制以便停止提供时钟信号。 因此，即使当内部电路中的延迟信号变得长于时钟信号的一个周期时，也可以防止发生错误的操作。