发明授权
US06201416B1 Field effect transistor logic circuit with reduced power consumption
失效
场效应晶体管逻辑电路具有降低的功耗
- 专利标题: Field effect transistor logic circuit with reduced power consumption
- 专利标题(中): 场效应晶体管逻辑电路具有降低的功耗
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申请号: US09276327申请日: 1999-03-25
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公开(公告)号: US06201416B1公开(公告)日: 2001-03-13
- 发明人: Keiichi Numata
- 申请人: Keiichi Numata
- 优先权: JP10-076374 19980325; JP10-243300 19980828
- 主分类号: H03K19084
- IPC分类号: H03K19084
摘要:
There is disclosed a field effect transistor logic circuit having an output terminal to be connected to a gate of an input field effect transistor in a next stage field effect transistor logic circuit. The field effect transistor logic circuit includes a depletion transistor having a drain connected to a first power supply voltage, an enhancement transistor having a drain connected at a node in common to a gate and a source of the depletion transistor. A gate of the enhancement transistor is connected to an input terminal, and a source of the enhancement transistor is connected to a second power supply voltage which is lower than the first power supply voltage. A high level potential limiting circuit is connected between the node and the output terminal, to lower a potential of the output terminal to a level which turns on a drain-source channel of the input field effect transistor of the next stage field effect transistor logic circuit but which never turns on a gate-source of the input field effect transistor of the next stage field effect transistor logic circuit, when the potential of the node is at a high level. A lower level lowering circuit having an input connected to the input terminal, is also connected between the output terminal and the second power supply voltage, for pulling down the potential of the output terminal to the potential of the second power supply voltage when the potential on the node is at a low level.
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