发明授权
US06202120B1 System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host bus
失效
用于在主机总线和系统存储器总线之间访问数据的系统和方法，其中系统存储器总线的数据路径是主机总线的数据路径宽度的两倍
- 专利标题： System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host bus
- 专利标题（中）： 用于在主机总线和系统存储器总线之间访问数据的系统和方法，其中系统存储器总线的数据路径是主机总线的数据路径宽度的两倍
-
申请号： US09364480申请日： 1999-07-30
-
公开(公告)号： US06202120B1公开(公告)日： 2001-03-13
- 发明人: Marilyn Jean Lang , Sridhar Begur , Robert Campbell , Carol Elise Bassett
- 申请人： Marilyn Jean Lang , Sridhar Begur , Robert Campbell , Carol Elise Bassett
- 主分类号： G06F1202
- IPC分类号： G06F1202
摘要：
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
信息查询
