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1.发明授权System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host bus 失效用于在主机总线和系统存储器总线之间访问数据的系统和方法，其中系统存储器总线的数据路径是主机总线的数据路径宽度的两倍公开(公告)号：US06202120B1
公开(公告)日：2001-03-13
申请号：US09364480
申请日：1999-07-30
IPC分类号： G06F1202
CPC分类号： G06F13/4243 , G06F12/0879
摘要： A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
摘要翻译： 微机系统存储器架构和方法允许系统存储器以突发模式以高速提供数据访问。 该架构和方法利用能够执行系统存储器寻址的系统存储器控制器。 微处理器和系统存储器通过高速主机总线进行通信。 系统存储器由多个64位系统存储器总线组成，以允许高速数据以突发模式传输到微处理器，而不需要外部高速缓存。
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公开(公告)号：US5732406A
公开(公告)日：1998-03-24
申请号：US950979
申请日：1992-09-23
CPC分类号： G06F13/28 , G06F12/0879 , G06F13/1631
摘要： A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.
摘要翻译： 微机架构和方法允许高处理速度。 微处理器构成中央处理单元。 微处理器包括片上缓存存储器，并且能够以突发模式读取数据。 中央处理单元和系统存储器通过高速主机总线进行通信。 系统存储器由多条总线组成，能够以突发模式高速传送数据给微处理器。 存储器控制器在从微处理器接收到第一主机地址时寻址系统存储器内的数据位置。 因此，当以突发模式操作时，微处理器可以以非常快的速率访问系统存储器中的数据。 高速处理完成，无需外部缓存。
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3.发明授权System and method for accessing data between a host bus and system memory buses in which each system memory bus has a data path which is twice the width of the data path for the host bus 失效用于在主机总线和系统存储器总线之间访问数据的系统和方法，其中每个系统存储器总线具有数据路径，该数据路径是主机总线的数据路径宽度的两倍
公开(公告)号：US5960450A
公开(公告)日：1999-09-28
申请号：US997620
申请日：1992-12-24
CPC分类号： G06F13/4243 , G06F12/0879
摘要： A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
摘要翻译： 微机系统存储器架构和方法允许系统存储器以突发模式以高速提供数据访问。 该架构和方法利用能够执行系统存储器寻址的系统存储器控制器。 微处理器和系统存储器通过高速主机总线进行通信。 系统存储器由多个64位系统存储器总线组成，以允许高速数据以突发模式传输到微处理器，而不需要外部高速缓存。
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