发明授权
US06207995B1 High K integration of gate dielectric with integrated spacer formation for high speed CMOS
有权
高K集成栅极电介质与高速CMOS的集成间隔物形成
- 专利标题: High K integration of gate dielectric with integrated spacer formation for high speed CMOS
- 专利标题(中): 高K集成栅极电介质与高速CMOS的集成间隔物形成
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申请号: US09255917申请日: 1999-02-23
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公开(公告)号: US06207995B1公开(公告)日: 2001-03-27
- 发明人: Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
- 申请人: Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
- 主分类号: H01L2976
- IPC分类号: H01L2976
摘要:
An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.
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