发明授权
- 专利标题： Memory circuit architecture
- 专利标题（中）： 内存电路架构
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申请号： US09425763申请日： 1999-10-22
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公开(公告)号： US06208551B1公开(公告)日： 2001-03-27
- 发明人: Hervé Jaouen , Richard Ferrant
- 申请人： Hervé Jaouen , Richard Ferrant
- 优先权： FR9813546 19981023
- 主分类号： G11C1124
- IPC分类号： G11C1124
摘要：
A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.
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