发明授权
US06218250B1 Method and apparatus for minimizing parasitic resistance of semiconductor devices
有权
用于最小化半导体器件的寄生电阻的方法和装置
- 专利标题: Method and apparatus for minimizing parasitic resistance of semiconductor devices
- 专利标题(中): 用于最小化半导体器件的寄生电阻的方法和装置
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申请号: US09324183申请日: 1999-06-02
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公开(公告)号: US06218250B1公开(公告)日: 2001-04-17
- 发明人: Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
- 申请人: Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.
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