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    Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors
    1.
    发明授权
    Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
    包括SOI晶体管和体晶体管的半导体器件的制造方法

    公开(公告)号：US07955937B2

    公开(公告)日：2011-06-07

    申请号：US11560896

    申请日：2006-11-17

    Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

    Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

    IPC: H01L21/331

    CPC classification number: H01L21/823481 ,  H01L21/76243 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207

    Abstract: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

    Abstract translation: 通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能 通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。 因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

    SOI transistor having a reduced body potential and a method of forming the same
    2.
    发明授权
    SOI transistor having a reduced body potential and a method of forming the same 有权
    具有降低的体电位的SOI晶体管及其形成方法

    公开(公告)号：US07863171B2

    公开(公告)日：2011-01-04

    申请号：US11609995

    申请日：2006-12-13

    Applicant: Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    Inventor： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    IPC: H01L21/00

    CPC classification number: H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

    Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

    Abstract translation: 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20100203698A1

    公开(公告)日：2010-08-12

    申请号：US12763324

    申请日：2010-04-20

    Applicant: Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    Inventor： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    IPC: H01L21/336

    CPC classification number: H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

    Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    4.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20100187635A1

    公开(公告)日：2010-07-29

    申请号：US12754819

    申请日：2010-04-06

    Applicant: SVEN BEYER ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    Inventor： SVEN BEYER ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    Abstract translation: 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    Method of forming a field effect transistor
    7.
    发明授权
    Method of forming a field effect transistor 有权
    形成场效应晶体管的方法

    公开(公告)号：US07723195B2

    公开(公告)日：2010-05-25

    申请号：US11566287

    申请日：2006-12-04

    Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC: H01L21/336

    CPC classification number: H01L29/66621 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

    Abstract translation: 形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。 在半导体材料的双轴应变层上形成栅电极。 在栅电极附近形成凸起的源区和升高的漏极区。 将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。 此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。 因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

    Field effect transistor and method of forming a field effect transistor
    9.
    发明授权
    Field effect transistor and method of forming a field effect transistor 有权
    场效应晶体管和形成场效应晶体管的方法

    公开(公告)号：US07629211B2

    公开(公告)日：2009-12-08

    申请号：US11684211

    申请日：2007-03-09

    Applicant: Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    Inventor： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    IPC: H01L21/331 ,  H01L21/8234

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

    Abstract translation: 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

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