The invention concerns a technique of a wiring processing method used in designing, for example, a large scale integrated circuit. The wiring processing method of the invention is provided with: a segment dividing step for dividing a wiring connecting between two receivers of a clock net into three or more segments; an equal delay branch segment determining step for comparing a first delay time from one branch point on one end of the segment to one receiver with a second delay time from the one branch point to the other receiver, and comparing a third delay time from the other branch point on the other end of the segment to the one receiver with a fourth delay time from the other branch point to the other receiver, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment; and an equal delay branch point determining step for determining an equal delay branch point in the equal delay branch segment. Thus, the equal delay branch point is accurately determined, and thereby the clock skew on the clock distributing circuit in a clock synchronous circuit is reduced.