公开(公告)号：US5889677A

公开(公告)日：1999-03-30

申请号：US574901

申请日：1995-12-19

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及 显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US07240317B2

公开(公告)日：2007-07-03

申请号：US10625554

申请日：2003-07-24

申请人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

发明人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associates with placements and wiring which are read out of a storage division and designated by user to the placement and wiring graphic information for display on a screen.

摘要翻译： 放置/网络布线处理系统使用交互式编辑器，其简化和简化了放置或移动单元格以及添加，删除或修改布线的操作。 布置/网络布线处理系统包括用于控制布局和布线操作和处理程序的执行的控制装置，用于在屏幕上显示布局和布线信息的显示装置，用于操作布局和布线的操作和处理装置 屏幕以及用于管理放置和布线信息的信息管理装置。 控制装置复制由此读出的程序，然后执行程序。 显示装置根据选择在屏幕上显示放置内容和布线图形信息，并且将处理相关信息与从存储部读出并由用户指定的放置和布线图形的布局和布线相关联 信息显示在屏幕上。

公开(公告)号：US06629305B2

公开(公告)日：2003-09-30

申请号：US09811772

申请日：2001-03-20

申请人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

发明人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out Thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associated with placements and wiring which are read out of a storage division and designated by the user to the placement and wiring graphic information for display on the screen.

摘要翻译： 放置/网络布线处理系统使用交互式编辑器，其简化和简化了放置或移动单元格以及添加，删除或修改布线的操作。 布置/网络布线处理系统包括用于控制布局和布线操作和处理程序的执行的控制装置，用于在屏幕上显示布局和布线信息的显示装置，用于操作布局和布线的操作和处理装置 屏幕以及用于管理放置和布线信息的信息管理装置。 控制装置复制由此读出的程序，然后执行程序。 显示装置根据选择在屏幕上显示放置内容和布线图形信息，并将与由存储部读出并由用户指定的布置和布线相关联的处理相关信息与放置和布线相关联 用于在屏幕上显示的图形信息。

公开(公告)号：US06223328B1

公开(公告)日：2001-04-24

申请号：US08896079

申请日：1997-07-17

申请人： Noriyuki Ito ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Toshihiko Tada

发明人： Noriyuki Ito ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Toshihiko Tada

IPC分类号： G06F1750

CPC分类号： G06F17/5077 ,  G06F1/10

摘要： The invention concerns a technique of a wiring processing method used in designing, for example, a large scale integrated circuit. The wiring processing method of the invention is provided with: a segment dividing step for dividing a wiring connecting between two receivers of a clock net into three or more segments; an equal delay branch segment determining step for comparing a first delay time from one branch point on one end of the segment to one receiver with a second delay time from the one branch point to the other receiver, and comparing a third delay time from the other branch point on the other end of the segment to the one receiver with a fourth delay time from the other branch point to the other receiver, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment; and an equal delay branch point determining step for determining an equal delay branch point in the equal delay branch segment. Thus, the equal delay branch point is accurately determined, and thereby the clock skew on the clock distributing circuit in a clock synchronous circuit is reduced.

摘要翻译： 本发明涉及用于设计例如大规模集成电路的布线处理方法的技术。 本发明的布线处理方法具有：分割步骤，用于将连接在时钟网络的两个接收器之间的布线分成三个或更多个段; 相等的延迟分支段确定步骤，用于将从所述段的一端的一个分支点的第一延迟时间与从所述一个分支点到另一个接收机的第二延迟时间的一个接收机进行比较，以及将来自所述另一个的第三延迟时间 在另一端的另一端的分支点到另一个接收机，具有从另一个分支点到另一个接收机的第四延迟时间，并且确定其中第一延迟时间的幅度相对于第二延迟时间和 相对于第四延迟时间的第三延迟时间被反转为相等的延迟分支段; 以及等距延迟分支点确定步骤，用于确定等延迟分支段中的等延迟分支点。 因此，等时延分支点被准确地确定，从而时钟同步电路中时钟分配电路的时钟偏移减小。

公开(公告)号：US20100077373A1

公开(公告)日：2010-03-25

申请号：US12559837

申请日：2009-09-15

申请人： Tomoyuki ISOMURA

发明人： Tomoyuki ISOMURA

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal figures, a logic element device wire protected area table, and a wire protected area table. A wire protected area creation unit adds an area of a terminal figure and a logic element device wire protected area obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number and acquires wire layer-via layer spacing information. A wiring information generating unit generates wiring information in the wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and wire protected area information.

摘要翻译： 布线信息生成装置包括：输入表示配线层的配线层号码，表示下一个通路层的通孔层号码以连接布线层的输入单元和基于布线规则的间隔信息​​。 存储单元存储提供终端图形的终端图表，逻辑单元设备线保护区表和有线保护区表。 有线保护区创建单元通过基于输入布线层号码和/或经由层号码搜索终端图表和逻辑元件设备线路保护区域表而获得的终端图形和逻辑元件设备线保护区域的区域 并获取有线层通过层间距信息。 布线信息生成单元基于半导体逻辑电路的连接信息和布置信息以及有线保护区域信息，在布线层中生成布线信息。

公开(公告)号：US08079010B2

公开(公告)日：2011-12-13

申请号：US12559837

申请日：2009-09-15

申请人： Tomoyuki Isomura

发明人： Tomoyuki Isomura

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal figures, a logic element device wire protected area table, and a wire protected area table. A wire protected area creation unit adds an area of a terminal figure and a logic element device wire protected area obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number and acquires wire layer-via layer spacing information. A wiring information generating unit generates wiring information in the wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and wire protected area information.

摘要翻译： 布线信息生成装置包括：输入表示配线层的配线层号码，表示下一个通路层的通孔层号码以连接配线层的输入单元和基于配线规则的间隔信息​​。 存储单元存储提供终端图形的终端图表，逻辑单元设备线保护区表和有线保护区表。 有线保护区创建单元通过基于输入布线层号码和/或经由层号码搜索终端图表和逻辑元件设备线路保护区域表而获得的终端图形和逻辑元件设备线保护区域的区域 并获取有线层通过层间距信息。 布线信息生成单元基于半导体逻辑电路的连接信息和布置信息以及有线保护区域信息，在布线层中生成布线信息。

公开(公告)号：US07240318B2

公开(公告)日：2007-07-03

申请号：US10625631

申请日：2003-07-24

申请人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

发明人： Noriyuki Ito ,  Ryoichi Yamashita ,  Keiko Osawa ,  Tomoyuki Isomura ,  Hiroaki Hanamitsu ,  Hideaki Katagiri

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associates with placements and wiring which are read out of a storage division and designated by user to the placement and wiring graphic information for display on a screen.

公开(公告)号：US06240541B1

公开(公告)日：2001-05-29

申请号：US09227967

申请日：1999-01-11

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制 单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。