发明授权
- 专利标题: Method to deposit a copper seed layer for dual damascene interconnects
- 专利标题(中): 沉积双层镶嵌铜层的方法
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申请号: US09501966申请日: 2000-02-10
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公开(公告)号: US06225221B1公开(公告)日: 2001-05-01
- 发明人: Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
- 申请人: Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
- 主分类号: H01L2144
- IPC分类号: H01L2144
摘要:
A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.
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