First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.