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公开(公告)号：US06534864B1
公开(公告)日：2003-03-18
申请号：US09428821
申请日：1999-10-28
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.
摘要翻译： 半导体存储器件（SRAM）包括存储单元，每个存储单元包括两个负载晶体管，两个驱动晶体管和两个转移晶体管。 SRAM单元包括其中形成晶体管的半导体衬底，形成在半导体衬底上的第一层间电介质，形成在第一层间电介质中的第一接触部分和形成在第一层间电介质上的第一布线层（节点布线层和衬垫层） 电介质。 第一接触部分和第一布线层包括由难熔金属制成的金属层和难熔金属氮化物层。 本发明的半导体存储器件能够提高布线层的集成度并实现微细加工。
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公开(公告)号：US06232670B1
公开(公告)日：2001-05-15
申请号：US09361043
申请日：1999-07-26
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.
摘要翻译： SRAM的第一和第二存储单元包括第一，第二和第三导电层。 第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。 第二导电层从场氧化物区域上的第一导电层发散，并且电连接到第二驱动器晶体管有源区。 第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。 第三导电层电连接到第一负载晶体管有源区。 第二存储单元的第一，第二和第三导电层的图案是第一存储单元中的第一，第二和第三导电层的旋转图案，围绕垂直于主表面的轴以180度的角度 的半导体衬底。
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公开(公告)号：US06300229B1
公开(公告)日：2001-10-09
申请号：US09563130
申请日：2000-05-02
IPC分类号： H01L2120
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer of an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成P型的第三杂质扩散层和N型的第四杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。
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公开(公告)号：US06243286B1
公开(公告)日：2001-06-05
申请号：US09361095
申请日：1999-07-26
IPC分类号： G11C1100
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An SRAM comprises first, second and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer branches from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The width of part of the second conductive layer on the field oxide region is less than the width of the first conductive layer.
摘要翻译： SRAM包括第一，第二和第三导电层。 第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。 第二导电层在场氧化物区域上从第一导电层分支并且电连接到第二驱动晶体管有源区。 第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。 第三导电层电连接到第一负载晶体管有源区。 场氧化物区域上的第二导电层的一部分的宽度小于第一导电层的宽度。
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公开(公告)号：US6081016A
公开(公告)日：2000-06-27
申请号：US282035
申请日：1999-03-30
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成N型的P型和第四杂质扩散层的第三杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。
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公开(公告)号：US06468850B2
公开(公告)日：2002-10-22
申请号：US09907097
申请日：2001-07-16
IPC分类号： H01L218238
CPC分类号： H01L27/105 , H01L27/1052
摘要： A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.
摘要翻译： 半导体器件具有具有外围电路区域和存储单元区域的半导体衬底。 在外围电路区域和存储单元区域之间形成具有第一导电性阱的边界区域。 在外围电路区域形成第二导电性阱。 外围电路区域中的阱与边界区域接触，但不与存储单元区域接触。 在边界区域形成虚拟晶体管。 虚拟晶体管被布置成与存储单元区域基本上相同的晶体管形成密度。
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公开(公告)号：US06320234B1
公开(公告)日：2001-11-20
申请号：US09450102
申请日：1999-11-29
IPC分类号： H01L2976
CPC分类号： H01L27/105 , H01L27/1052
摘要： A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.
摘要翻译： 半导体器件具有具有外围电路区域和存储单元区域的半导体衬底。 在外围电路区域和存储单元区域之间形成具有第一导电性阱的边界区域。 在外围电路区域形成第二导电性阱。 外围电路区域中的阱与边界区域接触，但不与存储单元区域接触。 在边界区域形成虚拟晶体管。 虚拟晶体管被布置成与存储单元区域基本上相同的晶体管形成密度。
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公开(公告)号：US20120019566A1
公开(公告)日：2012-01-26
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
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公开(公告)号：US08054710B2
公开(公告)日：2011-11-08
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C8/00
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
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公开(公告)号：US07986541B2
公开(公告)日：2011-07-26
申请号：US11270630
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G11C5/06
CPC分类号： G09G3/2007 , G09G2300/0426 , G09G2310/0267 , G09G2310/027 , G11C5/063
摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.
摘要翻译： 集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据，显示存储器包括多个RAM块，每个RAM块 包括多个字线，多个位线，多个存储器单元和字线控制电路，每个RAM块沿着位线延伸的第一方向设置，每个存储单元具有短边和 长边，沿着存储单元的长边延伸的方向形成位线，并且沿着存储单元的短边延伸的方向形成字线。
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