In the memory exclusive control device having a CPU-1 accessible to both a common memory and first memory devices, the CPU-1 is prohibited from accessing to the common memory device (105) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (111), the gate of the access permitting unit (103) is opened to thereby permit the CPU-1 to access to the common memory device (105). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.