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1.发明授权
公开(公告)号：US5153847A
公开(公告)日：1992-10-06
申请号：US599275
申请日：1990-10-16
CPC分类号： G06F7/544 , G06F7/4824 , G06F7/523 , G06F7/5338 , G06F7/5375
摘要： This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.
摘要翻译： 本发明公开了一种算术处理器，它将内部算术运算符表示为有符号位数，每个数字的数字可以具有正值，零值或负值，并且执行多个数字的加法，每个数字的最高有效位相对于 到其他数字。 算术处理器包括加法器树，该加法器树被相加以使得一对所述多个数字被相加以获得部分和，并且连续地添加另外的部分和对，以获得所有数字的最终和。 算术处理器还包括第一装置，用于添加两个数字存在的两个数字的一部分;第二装置，用于引起较低阶部分，其中只有一个数字存在的数字直接成为总和的一部分;第三装置， 保存或输出由第一装置产生的进位，以及第四装置，用于将加法器树的每个加法阶段中产生的进位加到加法器树的稍后的加法阶段以获得和。
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公开(公告)号：US06728806B2
公开(公告)日：2004-04-27
申请号：US09876106
申请日：2001-06-08
申请人： Toru Kakiage
发明人： Toru Kakiage
IPC分类号： G06F1338
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0677 , G11B20/10 , G11B20/18
摘要： In a data processing unit, improvement of the writing speed and efficiency of demodulated data from demodulating means into the buffer memory is achieved. As solving means thereof, writing of data demodulated in the demodulating means into the buffer memory is continuously performed after waiting for arrival of data of the same kind. Therefore, upon transfer of the demodulated data from the demodulating circuit to a temporary storage sub-means within the bus controller which controls access to the buffer memory, the kind of data of the next demodulated data is also transmitted.
摘要翻译： 在数据处理单元中，实现从解调装置向缓冲存储器提高解调数据的写入速度和效率。 作为其解决方法，在等待相同数据的到达之后，连续地将在解调装置中解调的数据写入缓冲存储器。 因此，在将解调数据从解调电路传送到控制对缓冲存储器的访问的总线控制器内的临时存储子装置的同时，也发送下一个解调数据的数据种类。
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公开(公告)号：US06573703B1
公开(公告)日：2003-06-03
申请号：US09543364
申请日：2000-04-05
申请人： Taichi Gyotoku , Toru Kakiage
发明人： Taichi Gyotoku , Toru Kakiage
IPC分类号： G01R3128
CPC分类号： G01R31/2879 , G01R31/2856 , G01R31/318572
摘要： A semiconductor for having a reduced required number of probes for inputting burn-in data to a target circuit, including two separate scan chains having respective first and second input terminals, and a selector for selecting one of first data from a first input terminal and second data from a second input terminal and supplying the selected first and second data to the second scan chain.
摘要翻译： 一种用于将目标电路输入老化数据所需数量减少的半导体，包括具有相应第一和第二输入端的两个单独的扫描链，以及用于从第一输入端和第二输入端选择第一数据之一的选择器 来自第二输入端的数据，并将所选择的第一和第二数据提供给第二扫描链。
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公开(公告)号：US06233663B1
公开(公告)日：2001-05-15
申请号：US09049108
申请日：1998-03-27
IPC分类号： G06F1202
CPC分类号： G06F13/1663
摘要： In the memory exclusive control device having a CPU-1 accessible to both a common memory and first memory devices, the CPU-1 is prohibited from accessing to the common memory device (105) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (111), the gate of the access permitting unit (103) is opened to thereby permit the CPU-1 to access to the common memory device (105). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.
摘要翻译： 在具有公共存储器和第一存储器件可访问的CPU-1的存储器独占控制装置中，在访问许可标志的OFF状态期间禁止CPU-1访问公共存储器件（105），并且当 访问许可标志ON由TCS（111）建立，访问许可单元（103）的门被打开，从而允许CPU-1访问公用存储设备（105）。 因此，可以实现存储器排他控制以将要处理的期望程序传送到第一存储器件的地址空间，从而允许省略第三存储器件。
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公开(公告)号：US06986095B2
公开(公告)日：2006-01-10
申请号：US09848218
申请日：2001-05-04
申请人： Toshinori Maeda , Toru Kakiage
发明人： Toshinori Maeda , Toru Kakiage
CPC分类号： G11B20/18
摘要： For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.
摘要翻译： 为了减少误差校正装置中纠错所需的时间，数据不仅从缓冲存储器传送到校正子计数器，而且同时传送到错误检测器，直到校正子计算器检测到含错误代码， 误差检测器与综合征计算器进行的综合征计算并行执行错误检测。 在错误校正器纠正误差之后的错误检测期间，使用在检测到含错误代码之前获得的错误检测的中期结果。 因此，不需要将所有数据从缓冲存储器传送到错误检测器，从而可以在中途执行错误检测处理。
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公开(公告)号：US5548249A
公开(公告)日：1996-08-20
申请号：US443577
申请日：1995-05-17
申请人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
发明人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
摘要： The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control circuit outputs two signals to the phase comparator as the first signal and the second signal, the phase difference between the two signals being substantially zero, and the voltage fixing control circuit fixing the voltage of the phase difference signal to a predetermined voltage at which the voltage control oscillator does not oscillate.
摘要翻译： 本发明的时钟发生器包括：输入切断控制电路，用于接收基准时钟和参考时钟，并响应复位信号输出第一信号和第二信号;相位比较器，用于输出指示相位的相位差信号 第一信号和第二信号之间的差; 电压控制振荡器，用于输出与所述相位差信号相对应的频率可变时钟; 以及电压固定控制电路，用于响应于所述复位信号来控制所述相位差信号的电压，其中，当所述复位信号处于第一电平时，所述输入关断控制电路将所述基准时钟输出到所述相位比较器 第一信号并将参考时钟作为第二信号输出到相位比较器，并且电压固定控制电路保持相位差信号的电压，并且当复位信号处于与第一电平不同的第二电平时，输入关断 控制电路将作为第一信号和第二信号的两个信号输出到相位比较器，两个信号之间的相位差基本为零，并且电压固定控制电路将相位差信号的电压固定为预定电压， 电压控制振荡器不振荡。
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公开(公告)号：US5537553A
公开(公告)日：1996-07-16
申请号：US149810
申请日：1993-11-10
申请人： Toru Kakiage
发明人： Toru Kakiage
CPC分类号： G06F12/0848
摘要： In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a signal between internal instruction and data buses and external bus. Upon concurrent miss of instruction cache and data cache, the bus controller executes an external instruction access with priority in case where the external instruction access is a same page access as a previous external DRAM access, and executes an external data access in the other cases. Thereby, the cycle number required for the external access is reduced, while reducing the number of instruction execution cycles as a total.
摘要翻译： 在具有中央处理单元，指令高速缓存和数据高速缓存的处理器中，提供总线控制器，用于控制内部指令与数据总线与外部总线之间的信号的提供和接收。 在同时缺席指令高速缓存和数据高速缓存时，总线控制器在外部指令访问与先前的外部DRAM访问相同的页面访问的情况下优先执行外部指令访问，并且在其他情况下执行外部数据访问。 因此，减少外部访问所需的周期数，同时减少指令执行周期的数量。
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公开(公告)号：US20060069977A1
公开(公告)日：2006-03-30
申请号：US11221346
申请日：2005-09-08
申请人： Toshinori Maeda , Toru Kakiage
发明人： Toshinori Maeda , Toru Kakiage
IPC分类号： H03M13/00
CPC分类号： G11B20/18
摘要： In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.
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9.发明授权Control systems having an address conversion device for controlling a cache memory and a cache tag memory 失效控制系统具有用于控制高速缓冲存储器的地址转换装置和高速缓存标签存储器
公开(公告)号：US5584003A
公开(公告)日：1996-12-10
申请号：US575265
申请日：1995-12-20
CPC分类号： G06F12/1054
摘要： A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.
摘要翻译： 用于控制高速缓存标签存储器的控制系统具有地址转换装置，其包括用于存储逻辑地址的关联存储器，用于存储物理地址的随机存取存储器和用于产生命中信号的命中信号产生电路，字选择信号 和至少一个控制信号。 命中信号指示在存储在关联存储器中的逻辑地址与输入逻辑地址之间发生命中。 地址转换装置通过使用由命中信号发生电路产生的控制信号与存储在存储器中的物理地址的读取操作中使用的字选择信号同步地控制存储在高速缓存标签存储器中的标签地址的读取操作 随机访问存储器，使得物理地址和标签地址在基本相同的时间被读取。 此外，该地址转换装置通过在同一时间读取物理地址和标签地址来控制存储在高速缓冲存储器中的数据的读取操作，并且通过使用由命中信号发生电路产生的第二控制信号与 字选择信号。 此外，地址转换装置控制从高速缓冲存储器的数据的读取和当物理地址与逻辑地址匹配时产生的高速缓存命中信号的产生。 因此，实现了高性能的系统。
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10.发明授权
公开(公告)号：US5206825A
公开(公告)日：1993-04-27
申请号：US857644
申请日：1992-03-24
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/5375
摘要： This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.
摘要翻译： 这是一个算术处理器，它将内部算术操作数表示为有符号位数，每个数字的数字可能具有正值，零值或负值，并且执行多个数字的加法，每个数字的最高有效位相对于 其他数字。 算术处理器包括加法器树，该加法器树被相加以使得一对所述多个数字被相加以获得部分和，并且连续地添加另外的部分和对，以获得所有数字的最终和。 算术处理器还包括第一装置，用于添加两个数字存在的两个数字的一部分;第二装置，用于引起较低阶部分，其中只有一个数字存在的数字直接成为总和的一部分;第三装置， 保存或输出由第一装置产生的进位，以及第四装置，用于将加法器树的每个加法阶段中产生的进位加到加法器树的稍后的加法阶段以获得和。
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