A memory integrated circuit (100) includes an array (102) of core cells (202) addressable by a plurality of word lines (120) and a plurality of drain lines (122). Address circuitry selects one or more word lines and one or more drain lines. Sensing circuit (110) senses a data state of one or more selected core cells of the array of core sells. Drain line charging circuitry charges one or more drain lines prior to sensing this data state. The drain line charging circuitry includes a rapid charging circuit (230) for precharging the one or more drain lines to the predetermined voltage during a precharge period, and a final charging circuit (214) for charging the one or more drain lines to a final charge voltage for sensing the data state.