An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.