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公开(公告)号：US06304487B1
公开(公告)日：2001-10-16
申请号：US09514404
申请日：2000-02-28
IPC分类号： G11C1606
CPC分类号： G11C16/12 , G11C16/10 , G11C16/3436
摘要： A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
摘要翻译： 编程或擦除存储器单元的电压控制电路包括内部电压值存储器，选择性地耦合到外部电压值源的寄存器器件或用于接收电压值的内部电压值存储器，耦合到寄存器器件的电压输出电路， 接收电压值并将相应的电压输出到存储器单元，以及确认电路确定成功编程或擦除存储单元的时间。 寄存器件允许用由外部电压值源指定的电压值对存储器单元进行编程或擦除，以确定存储器单元的编程和擦除特性。 产生可接受的编程和擦除特性的电压值被保存在内部电压值存储器中。
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公开(公告)号：US06246611B1
公开(公告)日：2001-06-12
申请号：US09514560
申请日：2000-02-28
IPC分类号： G11C1600
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.
摘要翻译： 擦除控制电路根据可由测试设备改变的擦除信号值来擦除存储单元。 擦除控制电路包括信号存储装置，信号输出电路和验证电路。 信号存储装置存储擦除信号值。 测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。 信号输出电路耦合到信号存储装置以接收擦除信号值。 信号输出电路将擦除信号值转换成擦除信号，并将该擦除信号输出到存储单元。 验证电路确定存储器单元是否被成功擦除。 如果存储单元未成功擦除，则擦除控制电路增加擦除信号值。
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公开(公告)号：US06295228B1
公开(公告)日：2001-09-25
申请号：US09514933
申请日：2000-02-28
IPC分类号： G11C1606
CPC分类号： G11C29/028 , G11C16/04 , G11C16/10 , G11C16/30 , G11C29/50 , G11C2029/5004
摘要： A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.
摘要翻译： 编程控制电路根据可由测试设备改变的编程信号值对存储器单元进行编程。 编程控制电路包括信号存储装置，信号输出电路和验证电路。 信号存储装置存储编程信号值。 测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。 信号输出电路耦合到信号存储装置以接收编程信号值。 信号输出电路将编程信号值转换为编程信号，并将编程信号输出到存储单元。 验证电路确定存储器单元是否被成功编程。 如果存储单元未成功编程，编程控制电路会增加编程信号值。
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公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。
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公开(公告)号：US06643177B1
公开(公告)日：2003-11-04
申请号：US10349293
申请日：2003-01-21
申请人： Binh Quang Le , Pau-Ling Chen
发明人： Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1628
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0475 , G11C16/28 , G11C2211/5634
摘要： A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.
摘要翻译： 一种用于为闪存单元阵列中的动态参考阵列提供修改的阈值电压分布的方法。 使用两个不同的编程过程对动态参考阵列和相关联的核心存储器单元阵列进行编程，以为动态参考阵列和核心存储器单元阵列产生不同的Vt分布。 使用更精细的编程脉冲对动态参考阵列进行编程，以实现更小的分布宽度，从而增强存储单元阵列的读取余量。 较细的脉冲可以具有较短的持续时间或较小的振幅。 更精细的编程过程可以应用于存储单元阵列中的一个或多个阈值电压分布（状态）。
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公开(公告)号：US06269025B1
公开(公告)日：2001-07-31
申请号：US09500699
申请日：2000-02-09
申请人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1604
摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.
摘要翻译： 如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。 存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。 电压值存储装置存储电压值。 电压源接收并将电压值转换为电压。 电压源将电压施加到至少一个存储单元。 电压调节电路也耦合以接收存储的电压值。 电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。 如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。
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7.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 失效具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
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8.发明授权Method and system for defining a redundancy window around a particular column in a memory array 有权用于在存储器阵列中的特定列周围定义冗余窗口的方法和系统公开(公告)号：US07076703B1
公开(公告)日：2006-07-11
申请号：US10305700
申请日：2002-11-26
申请人： Binh Quang Le , Pau-Ling Chen
发明人： Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/804
摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.
摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。
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9.发明授权Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider 有权使用电容分压器连续调节电荷泵输出电压的方法和装置公开(公告)号：US06288951B1
公开(公告)日：2001-09-11
申请号：US09675940
申请日：2000-09-29
申请人： Pau-Ling Chen , Binh Quang Le
发明人： Pau-Ling Chen , Binh Quang Le
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.
摘要翻译： 一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。
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10.发明授权Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor 失效用于具有浮置晶体管作为相应电容器的电容分压器中的电容器公开(公告)号：US06262469B1
公开(公告)日：2001-07-17
申请号：US09047237
申请日：1998-03-25
IPC分类号： H01L2900
CPC分类号： H01L29/94 , H01L27/0811 , H01L29/66189
摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.
摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。
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