Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition

发明授权

US06251753B1 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition 有权

标题翻译：通过选择性液相沉积对低介电常数电介质的无降解镶嵌沟槽进行侧壁封盖的方法

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专利标题： Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition
专利标题（中）： 通过选择性液相沉积对低介电常数电介质的无降解镶嵌沟槽进行侧壁封盖的方法
申请号： US09447715

申请日： 1999-11-23
公开(公告)号： US06251753B1

公开(公告)日： 2001-06-26
发明人: Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
主分类号： H01L2176
IPC分类号： H01L2176

Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition

摘要：

A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.

摘要（中）：

用作层间电介质的低介电常数（k）材料，如甲基倍半硅氧烷（MSQ），有望降低集成电路中的寄生电容。然而，在蚀刻形成镶嵌的沟槽之后的抗蚀剂灰化过程中，MSQ膜可以容易地劣化。本发明公开了一种创新的侧壁封盖技术来解决退化问题。在抗蚀灰化之前，使用选择性液相沉积将高质量，低k氧化物膜选择性地沉积在MSQ沟槽的侧壁上。实验结果表明，覆盖氧化物可以有效地保护MSQ沟槽的侧壁免受灰分诱导的退化。

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