PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.