公开(公告)号：US06531927B1

公开(公告)日：2003-03-11

申请号：US09677623

申请日：2000-10-03

申请人： Dao-Long Chen

发明人： Dao-Long Chen

IPC分类号： H03L7089

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091

摘要： The present invention discloses a novel method and apparatus for making a jitter transfer function of a phase-locked loop independent from the data transition density. The present invention is further discloses a phase-locked loop which has a loop bandwidth and a loop gain in the passband which are both independent from the received data patterns. By making the loop bandwidth independent of the received data pattern, the noise filtering performance of the phase-locked loop may be optimized.

摘要翻译： 本发明公开了一种独立于数据转换密度的锁相环的抖动传递函数的新方法和装置。 本发明进一步公开了一种锁相环，该锁相环具有通带中的环路带宽和环路增益，两者均独立于所接收的数据模式。 通过使环路带宽与接收的数据模式无关，可以优化锁相环的噪声滤波性能。

公开(公告)号：US06415007B1

公开(公告)日：2002-07-02

申请号：US09163084

申请日：1998-09-29

申请人： Atsushi Kawasumi

发明人： Atsushi Kawasumi

IPC分类号： H03L7089

CPC分类号： G11C7/1066 ,  G11C5/145 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H02M3/07 ,  H03L7/0895 ,  H03L7/0995

摘要： A charge pump according to the invention has first and second sub charge pumps which include a common charging/discharging terminal and perform charging/discharging operations. When the first sub charge pump is operated, and electricity to be offset is charged or discharged due to a junction capacitor located at a PN junction which exists between transistors included in the first sub charge pump, the second sub charge pump performs a discharging operation if the electricity is charged, and a charging operation if it is discharged, in order to offset the electricity. Moreover, while the first sub charge pump performs a charging operation, the second sub charge pump performs a charging operation for a time period shorter by a predetermined time period than the charging period of the first sub charge pump. On the other hand, while the first sub charge pump performs a discharging operation, the second sub charge pump performs a discharging operation for a time period shorter by a predetermined time period than the discharging period of the first sub charge pump.

摘要翻译： 根据本发明的电荷泵具有包括公共充电/放电端子并执行充电/放电操作的第一和第二副电荷泵。 当操作第一副电荷泵时，由于存在于包含在第一副电荷泵中的晶体管之间的PN结处的结电容器而使要偏移的电力被充电或放电，所以第二副电荷泵执行放电操作，如果 电力充电，并且如果其被放电，则进行充电操作，以便抵消电力。 此外，当第一副电荷泵进行充电操作时，第二副电荷泵在比第一副电荷泵的充电时间短一个预定时间段的时间段内执行充电操作。 另一方面，当第一副电荷泵执行放电操作时，第二副电荷泵在比第一副电荷泵的放电期间短预定时间段的时间段内执行放电操作。

公开(公告)号：US06424230B1

公开(公告)日：2002-07-23

申请号：US09676524

申请日：2000-09-29

申请人： Namik K. Kocaman ,  Michael W. Altmann

发明人： Namik K. Kocaman ,  Michael W. Altmann

IPC分类号： H03L7089

CPC分类号： H03L7/099

摘要： A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems. To counter the coupling of the parasitic gain, an inverted gain is inserted from the amplitude control loop into the phase/frequency control loop in opposite to the parasitic gain, so as to effectively cancel the interference. The circuit and method also provide for canceling the opposite parasitic gain that is coupled from the phase/frequency loop into the amplitude control loop.

摘要翻译： 一种锁相环电路和方法，其基本上分离了相位/频率的控制和振荡输出的幅度，使得可以独立于振幅来控制振荡的频率。 锁相环电路包括相位/频率控制环路和幅度控制环路，其中两个环路响应于由相位/频率控制环路产生的相位/频率控制信号以一定频率振荡的振荡器。 此外，振荡幅度由振幅控制回路产生的振幅控制信号决定。 与这种类型的常规电路一样，寄生增益从幅度控制环路耦合到相位/频率控制环路中，从而引起环路之间的干扰，从而导致稳定性问题。 为了对抗寄生增益的耦合，将反向增益从振幅控制环路插入与寄生增益相反的相位/频率控制环路中，以有效地消除干扰。 电路和方法还提供消除从相位/频率环路耦合到幅度控制环路中的相反的寄生增益。

公开(公告)号：US06346861B2

公开(公告)日：2002-02-12

申请号：US09733837

申请日：2000-12-07

申请人： Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

发明人： Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

IPC分类号： H03L7089

CPC分类号： H03L7/107 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/18

摘要： A phase locked loop (PLL) is use in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

摘要翻译： 锁相环（PLL）在诸如混频器，载波频率等的无线电通信系统中使用。 锁相环（PLL）包括用于比较参考信号的相位/频率和反馈信号的相位/频率检测器。 相位/频率检测器包括：与非门逻辑电路，用于对第一信号进行NAND和第二信号以输出NAND信号; 第一锁存单元，用于锁存所述NAND信号并响应于参考频率输出所述第一信号; 以及第二锁存单元，用于锁存所述NAND信号并响应于反馈频率输出所述第二信号。 锁相环（PLL）还包括滤波器控制器，用于响应于相位/频率检测器的输出信号来改变低通滤波器的带宽。

公开(公告)号：US06252466B1

公开(公告)日：2001-06-26

申请号：US09547818

申请日：2000-04-11

申请人： J. Patrick Kawamura

发明人： J. Patrick Kawamura

IPC分类号： H03L7089

CPC分类号： H03L7/095 ,  H03L7/0891 ,  Y10S331/02

摘要： PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.

摘要翻译： PLL上电检测器包括耦合到充电电路的电容器。 电容器被充电到响应于包括在PLL电路中的PFD电路产生的UP和DOWN信号的脉冲宽度的电平。 当PLL接近或处于锁定状态时，UP和DOWN信号将呈现短暂的高电平脉冲或保持在地电平，从而允许充电器电路增加电容器上的电压。 施密特触发电路检测电容器上的电压电平，并输出指示PLL接近或处于锁定状态的信号。 施密特触发器输出信号耦合到计数器电路，以进一步验证PLL的锁定状态。 在施加PLL上电信号之前，施密特触发输出信号必须保持在n个连续参考时钟周期的锁定状态。 当上电信号置位时，充电电路被禁止，PLL上电检测器不会消耗静态电流。

公开(公告)号：US06771133B2

公开(公告)日：2004-08-03

申请号：US10170160

申请日：2002-06-12

申请人： Lloyd L. Lautzenhiser

发明人： Lloyd L. Lautzenhiser

IPC分类号： H03L7089

CPC分类号： H03L7/189

摘要： Phase-locked oscillators (74, 152, 172, or 196) include both a digital integrator (82 or 146) and a digital lead compensator (84, 148, or 180), and use either analog (108) or digital (184) summation of integration and lead-compensation signals to provide a lead-compensated digital integrator (86, 150, or 182). Preferably, integration and/or lead compensation includes decoding UP and DOWN signals into plus one, minus one, and/or zero signals. The phase-locked oscillators (74, 152, 172, or 196) may include one or more nonlinear digital-to-analog converters (282, 292, 310, 340, or 370) for digital-to-analog converting the digital phase-locking information and the digital lead-compensation information.

摘要翻译： 锁相振荡器（74,152,172或196）包括数字积分器（82或146）和数字引线补偿器（84,148或180），并且使用模拟（108）或数字（184） 积分和前置补偿信号的总和，提供一个先导补偿数字积分器（86,150或182）。 优选地，积分和/或引导补偿包括将UP和DOWN信号解码为加1，减1和/或零信号。 锁相振荡器（74,152,172或196）可以包括一个或多个非线性数模转换器（282,292,310,340或370），用于数模转换数字相位 - 锁定信息和数字引导补偿信息。

公开(公告)号：US06734739B2

公开(公告)日：2004-05-11

申请号：US10283119

申请日：2002-10-30

申请人： Tadashi Kawahara

发明人： Tadashi Kawahara

IPC分类号： H03L7089

CPC分类号： H03C3/0925 ,  H03D13/004 ,  H03L7/0898 ,  H03L7/1976

摘要： The phase comparator in a phase locked loop synthesizer has a identical first and second transmission gates connected to a front row and a back row of 2N−1 gate delay elements, respectively. Third and fourth transmission gates are permanently set to an ON setting. The first transmission gate and NAND gates operate as a gate delay element when a COUNT signal is at a low logical level and operate as a ring oscillator when the COUNT signal is at a high logical level.

摘要翻译： 锁相环合成器中的相位比较器具有相同的第一和第二传输门，分别连接到前排和后排的2N-1个门延迟元件。 第三和第四传输门永久地设置为ON设置。 当COUNT信号处于低逻辑电平并且当COUNT信号处于高逻辑电平时，第一传输门和NAND门用作门延迟元件，并作为环形振荡器工作。

公开(公告)号：US06424180B1

公开(公告)日：2002-07-23

申请号：US09780663

申请日：2001-02-08

申请人： Ray Killorn

发明人： Ray Killorn

IPC分类号： H03L7089

CPC分类号： H03L7/087 ,  H03D13/003 ,  H03L7/0891

摘要： A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. In one embodiment, the present invention relates to a digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier. The amount of phase shift between the clock signals impacts the position of nominal times in the metastable region. In addition, the greater the number of flip flops in the detection circuit that are coupled to clock signals that trigger the flip flop at a different time from any other flip flop in the detection unit, the greater the ability to differentiate and proportional sensitivity the present embodiment has to small timing differences in an input signal.

摘要翻译： 数字相移放大和检测系统及方法。 信号被施加到数字相移放大器，其包括在亚稳态区域中操作的触发器，该触发器放大信号中的任何定时变化。 被放大的信号被馈送到被配置为检测放大信号中的定时延迟的检测电路。 在一个实施例中，本发明涉及数字相移放大和检测系统和方法。 信号被施加到数字相移放大器，其包括在亚稳态区域中操作的触发器，该触发器放大信号中的任何定时变化。 被放大的信号被馈送到检测电路，该检测电路被配置为由于输入信号中的相对较小的定时改变而检测放大的信号中的放大的定时差。 检测电路耦合到触发相移放大器中的亚稳触发器的时钟信号异相的时钟信号。 时钟信号之间的相移量影响亚稳态区域中标称时间的位置。 此外，与检测单元中的任何其它触发器不同的时间触发触发器的时钟信号耦合到检测电路中的触发器的数量越多，目前的区分和比例灵敏度的能力越大 实施例必须在输入信号中具有小的定时差。

公开(公告)号：US06417738B1

公开(公告)日：2002-07-09

申请号：US09353406

申请日：1999-07-15

申请人： Lloyd L. Lautzenhiser

发明人： Lloyd L. Lautzenhiser

IPC分类号： H03L7089

CPC分类号： H03L7/189

摘要： A frequency-hopping oscillator (72, 136, 170, or 190) includes a phase-locked oscillator (74, 152, 172, or 196). The phase-locked oscillator (74, 152, 172, or 196) includes both a digital integrator (82 or 146) and a lead compensator (84, 148, or 180), and uses either analog (108) or digital (184) summation of integration and lead-compensation signals to provide a lead-compensated digital integrator (86, 150, or 182). The frequency-hopping oscillator (72, 136, 170, or 190) is adaptive in that it develops channelizing voltage via analog components, such as a VCO 20 and an improved D/A converter 98. The improved D/A converter 98 is designed to prevent “holes” even if a larger number of bits are processed using low-precision resistors. The improved D/A converter 98 is further characterized as being nonlinear (286), producing a lower output voltage (280) by a higher bit than by a total output voltage (278) produced by all lower bits, and producing an output voltage by one bit that is less than twice the output voltage of the next lower bit.

摘要翻译： 跳频振荡器（72,136,170或190）包括锁相振荡器（74,152,172或196）。 锁相振荡器（74,152,172或196）包括数字积分器（82或146）和引线补偿器（84,148或180），并且使用模拟（108）或数字（184） 积分和前置补偿信号的总和，提供一个先导补偿数字积分器（86,150或182）。 跳频振荡器（72,136,170或190）是自适应的，因为其通过诸如VCO 20和改进的D / A转换器98的模拟组件来产生信道化电压。改进的D / A转换器98被设计 即使使用低精度电阻处理较大数量的位，也可以防止“漏洞”。 改进的D / A转换器98进一步被表征为非线性（286），通过比由所有低位产生的总输出电压（278）产生较高的位，产生较低的输出电压（280），并且通过 一位小于下一位低位输出电压的两倍。

公开(公告)号：US06741102B1

公开(公告)日：2004-05-25

申请号：US09300757

申请日：1999-04-26

申请人： Thomas P. Thomas

发明人： Thomas P. Thomas

IPC分类号： H03L7089

CPC分类号： H03L7/089 ,  H03D13/004 ,  H03L7/183

摘要： Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

摘要翻译： 简而言之，根据一个实施例，集成电路包括包括两个时钟输入端口，上行信号端口和下行信号端口的相位频率检测器（PFD）。 PFD包括数字电路，其包括以配置来耦合的晶体管，以至少部分地基于两个相应时钟信号之间的相位延迟量的大小来调整上输出信号脉冲和下输出信号脉冲的重叠量 施加到两个输入端口的脉冲。 当然，还公开了另外的实施例。