发明授权
US06252821B1 Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices
有权
用于支持大量存储器件的存储器子系统中的存储器地址解码的方法和装置
- 专利标题： Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices
- 专利标题（中）： 用于支持大量存储器件的存储器子系统中的存储器地址解码的方法和装置
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申请号： US09474570申请日： 1999-12-29
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公开(公告)号： US06252821B1公开(公告)日： 2001-06-26
- 发明人: Puthiya K. Nizar , Michael W. Williams
- 申请人： Puthiya K. Nizar , Michael W. Williams
- 主分类号： G11C800
- IPC分类号： G11C800
摘要：
One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group of memory devices, each of the memory devices in the group having the same configuration. A group number is generated that represents an addressed group that contains an addressed memory device that contains the memory access address. A device number is generated that represents the location of the addressed memory device within the addressed group. A device selection signal is generated responsive to the group number and the device number.
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