公开(公告)号：US06829194B2

公开(公告)日：2004-12-07

申请号：US10307283

申请日：2002-12-02

申请人： Yasuhiko Honda ,  Hideo Kato ,  Hidetoshi Saito ,  Masao Kuriyama ,  Tokumasa Hara ,  Takafumi Ikeda ,  Tatsuya Hiramatsu

发明人： Yasuhiko Honda ,  Hideo Kato ,  Hidetoshi Saito ,  Masao Kuriyama ,  Tokumasa Hara ,  Takafumi Ikeda ,  Tatsuya Hiramatsu

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

摘要翻译： 半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体 设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器 和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

公开(公告)号：US06826115B2

公开(公告)日：2004-11-30

申请号：US10640146

申请日：2003-08-13

申请人： Jung-Bae Lee ,  Yun-Sang Lee

发明人： Jung-Bae Lee ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/1021 ,  G11C8/10 ,  G11C8/12

摘要： A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.

公开(公告)号：US06826112B2

公开(公告)日：2004-11-30

申请号：US10347723

申请日：2003-01-21

申请人： Joseph Ku ,  James Robert Eaton

发明人： Joseph Ku ,  James Robert Eaton

IPC分类号： G11C800

CPC分类号： H03K19/096 ,  H03K19/12

摘要： The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines. The plurality of address lines are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.

公开(公告)号：US06809986B2

公开(公告)日：2004-10-26

申请号：US10232953

申请日：2002-08-29

申请人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

发明人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

摘要翻译： 负字线驱动器使用器件来维持有源字线信号和非活动字线信号之间的电位差，同时减少对显着的负电压电源的需要。 当字线驱动器的输入指示字线不应该被激活，同时字线也耦合到负电压源时，一种形式的负字线驱动器采用隔离元件将字线耦合到地。 负字形线驱动器的形式的另一种形式作为输入端接收要在字线上驱动的电压，并且可以用较少的晶体管来实现，但是仍然允许字线在负电压下以负电压供给被驱动。

公开(公告)号：US06809983B2

公开(公告)日：2004-10-26

申请号：US10397483

申请日：2003-03-25

申请人： Chang Ho Jung

发明人： Chang Ho Jung

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22

摘要： A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

摘要翻译： 用于伪双端口存储器的时钟产生电路包含反馈，延迟和锁存器，以确保写（读）操作时钟脉冲在时间上与读（写）操作时钟充分间隔开。 时钟产生电路接收外部时钟，读使能信号，写使能信号和复位信号作为输入。 优点包括最小化时钟周期时间和不受外部时钟占空比的影响。 可以添加延迟电路，使得所生成的时钟信号具有足够的扇出并且足够稳定。

公开(公告)号：US06798712B2

公开(公告)日：2004-09-28

申请号：US10190372

申请日：2002-07-02

申请人： Bruce Alan Gieseke ,  William A. McGee ,  Ognjen Milic-Strkalj

发明人： Bruce Alan Gieseke ,  William A. McGee ,  Ognjen Milic-Strkalj

IPC分类号： G11C800

CPC分类号： G11C8/16 ,  G11C8/06

摘要： A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

摘要翻译： 提供了一种存储器系统及其操作方法，其具有用于存储数据的存储单元，用于将数据写入并从存储器单元读取数据的位线，以及连接到存储器单元的字线，用于使位线将数据写入存储器单元 响应于字线信号。 解码器连接到字线，用于响应于时钟信号和地址信号接收和解码地址信息，以选择用于写入存储器单元的字线。 锁存电路连接到解码器和字线。 锁存电路响应于时钟信号，用于将字线信号提供给所选择的字线以用于对存储器单元的写入，并且当对存储器单元的写入完成时从所选择的字线中去除字线信号。

公开(公告)号：US06791898B1

公开(公告)日：2004-09-14

申请号：US10269391

申请日：2002-10-11

申请人： Rajesh Manapat ,  Manoj Roge ,  Kannan Srinivasagam

发明人： Rajesh Manapat ,  Manoj Roge ,  Kannan Srinivasagam

IPC分类号： G11C800

CPC分类号： G11C7/1072 ,  G11C7/1021 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/22

摘要： Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determine other functionalities of the particular data transfer mode. Functionalities may include normal and page mode, page length, bust read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.

摘要翻译： 本发明的实施例提供具有多种数据传输模式的存储器件。 在一个实施例中，异步/同步逻辑和配置寄存器提供异步和同步数据传输。 异步/同步逻辑利用配置寄存器和各种控制信号来确定数据传输操作是否应该是异步或同步的。 异步/同步逻辑还利用配置寄存器和各种控制信号来确定特定数据传输模式的其他功能。 功能可以包括正常和页面模式，页面长度，胸围读取，线性或交织突发，突发包，突发挂起，数据保持长度，第一访问延迟，同步和异步模式之间的转换等。

公开(公告)号：US06778464B2

公开(公告)日：2004-08-17

申请号：US10288830

申请日：2002-11-06

申请人： Dae-hyun Chung

发明人： Dae-hyun Chung

IPC分类号： G11C800

CPC分类号： G11C7/1093 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087

摘要： Synchronous semiconductor memory devices and methods of operating are provided. The device has a latency N and includes a memory cell array, a stack unit having N storage units and a frequency detector that provides an output signal based on the relationship of the frequency of operation clock to a predetermined frequency. A control circuit controls the stack unit in response to the output signal of the frequency detector. The control circuit latches data read from the memory and controls the stack unit so that the latched data is stored from a clock cycle when a read command is sent until an N-th cycle afterwards if the clock frequency is greater than the predetermined frequency and delays the latched data for one cycle and controls the stack unit so that the delayed data is stored from one cycle after the read command is sent until an N+1 cycle afterwards.

摘要翻译： 提供了同步半导体存储器件和操作方法。 该设备具有延迟N，并且包括存储单元阵列，具有N个存储单元的堆叠单元和基于操作时钟频率与预定频率的关系提供输出信号的频率检测器。 控制电路根据频率检测器的输出信号控制堆栈单元。 控制电路锁存从存储器读取的数据并控制堆栈单元，使得当读命令被发送到第N个周期之后，如果时钟频率大于预定频率并且延迟，则从锁存数据存储从时钟周期 一个周期的锁存数据并控制堆栈单元，以便在发送读命令之后从一个周期开始存储延迟的数据，直到N + 1个周期后。

公开(公告)号：US06771555B2

公开(公告)日：2004-08-03

申请号：US10152705

申请日：2002-05-22

申请人： Sang Hee Kang

发明人： Sang Hee Kang

IPC分类号： G11C800

CPC分类号： G11C29/80

摘要： Row access information transfer devices and methods are disclosed which use an internal wiring of a memory cell array to transfer information to a column fuse box array. The disclosed techniques and structures can increase the efficiency of a circuit by transferring sense amplifier and wordline control signals relating to a specific row block corresponding to an inputted row address to a column fuse box array using wiring within the cell array, when the row block is accessed in DRAM.

摘要翻译： 公开了使用存储单元阵列的内部布线将信息传送到列保险丝盒阵列的行访问信息传送设备和方法。 所公开的技术和结构可以通过将读取放大器和与输入的行地址相对应的特定行块相关的字线控制信号传送到列保险丝盒阵列来增加电路的效率，使用单元阵列内的布线，当行块为 在DRAM中访问

公开(公告)号：US06765842B2

公开(公告)日：2004-07-20

申请号：US10331791

申请日：2002-12-30

申请人： Kwan-Weon Kim

发明人： Kwan-Weon Kim

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A hole driver for driving a hole in a semiconductor memory device, including a first bank controller for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank, a second bank controller for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank, a block address enable means for generating a common block address enable signal in response to output signals of the first and the second bank control means and a common block address predecoder for predecoding block address signal for each bank in response to the common block address enable signal.

摘要翻译： 一种用于在半导体存储器件中驱动孔的孔驱动器，包括：第一存储体控制器，用于响应于行有源信号和用于第一存储体的预充电信号产生用于控制第一存储体的X孔的控制信号; 第二组控制器，用于响应于行活动信号和用于第二组的预充电信号产生用于控制第二组的X孔的控制信号;块地址使能装置，用于响应于第二组控制信号产生公共块地址使能信号 第一和第二组控制装置的输出信号和用于响应于公共块地址使能信号为每个组预测编码块地址信号的公共块地址预解码器。