发明授权
US06256720B1 High performance, superscalar-based computer system with out-of-order instruction execution
失效
高性能,基于超标量的计算机系统,执行无序指令
- 专利标题: High performance, superscalar-based computer system with out-of-order instruction execution
- 专利标题(中): 高性能,基于超标量的计算机系统,执行无序指令
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申请号: US09436986申请日: 1999-11-09
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公开(公告)号: US06256720B1公开(公告)日: 2001-07-03
- 发明人: Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
- 申请人: Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
- 主分类号: G06F930
- IPC分类号: G06F930
摘要:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.