公开(公告)号：US07739482B2

公开(公告)日：2010-06-15

申请号：US11642599

申请日：2006-12-21

Applicant: Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

Inventor： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC: G06F15/76

CPC classification number: G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US07162610B2

公开(公告)日：2007-01-09

申请号：US10660671

申请日：2003-09-12

Applicant: Le Trong Nguyen ,  Derek J Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H Trang

Inventor： Le Trong Nguyen ,  Derek J Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H Trang

IPC: G06F15/78 ,  G06F9/38 ,  G06F9/40

CPC classification number: G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US20050251653A1

公开(公告)日：2005-11-10

申请号：US11167289

申请日：2005-06-28

Applicant: Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

Inventor： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

IPC: C10G1/00 ,  C10G17/02 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/76

CPC classification number: G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

公开(公告)号：US06611908B2

公开(公告)日：2003-08-26

申请号：US09884943

申请日：2001-06-21

Applicant: Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

Inventor： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

IPC: G06F1314

CPC classification number: G06F12/0813 ,  G06F12/0215 ,  G06F12/0831 ,  G06F12/0855 ,  G06F13/18 ,  G06F13/4022 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract translation: 一种存储器控制单元，用于通过处理器的一个或多个存储器端口控制由处理器内的一个或多个设备到处理器外部的存储器阵列单元的访问。 存储器控制单元包括交换网络，用于在处理器的一个或多个设备与处理器的一个或多个存储器端口之间传送数据。 存储器控制单元还包括用于仲裁交换网络的交换仲裁单元和用于仲裁一个或多个存储器端口的端口仲裁单元。

公开(公告)号：US06289433B1

公开(公告)日：2001-09-11

申请号：US09329354

申请日：1999-06-10

Applicant: Sanjiv Garg ,  Kevin Ray Iadonato ,  Le Trong Nguyen ,  Johannes Wang

Inventor： Sanjiv Garg ,  Kevin Ray Iadonato ,  Le Trong Nguyen ,  Johannes Wang

IPC: G06F1500

CPC classification number: G06F9/3013 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependence check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract translation: 一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件， 存储指令操作数。 包括用于确定指令之间的数据依赖性的数据相关性检查电路。 标签分配电路根据由数据相关性检查电路确定的数据相关性，生成更多标签之一以指定操作数的位置。 一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

公开(公告)号：US06272579B1

公开(公告)日：2001-08-07

申请号：US09253761

申请日：1999-02-22

Applicant: Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

Inventor： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

IPC: G06F1314

CPC classification number: G06F12/0813 ,  G06F12/0215 ,  G06F12/0831 ,  G06F12/0855 ,  G06F13/18 ,  G06F13/4022 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173

Abstract: A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

Abstract translation: 用于在能够支持多个处理器的多处理器架构中传送数据的系统和方法。 该系统包括优先级分配器，该优先级分配器根据分配给每个设备的内在优先级向输入/输出单元（IOU），D-缓存和I缓存设备请求提供动态优先级，并且包括存在一个 所请求的地址和先前服务的请求之间的行匹配，设备被拒绝服务的次数以及设备未被中断的次数。 该系统还包括跟踪器以跟踪每个因素发生的次数，以及优先级改变器，以根据内在优先级和数量来改变设备的优先级。

公开(公告)号：US06256720B1

公开(公告)日：2001-07-03

申请号：US09436986

申请日：1999-11-09

Applicant: Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

Inventor： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC: G06F930

CPC classification number: G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract translation: 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US6038653A

公开(公告)日：2000-03-14

申请号：US158568

申请日：1998-09-22

Applicant: Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

Inventor： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across mutliple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

Abstract translation: 高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。 提取单元通常在指令缓冲器中保持预定数量的指令。 执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。 在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。 在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要对数据执行的计算函数类型进行优化：整数，浮点和布尔值。 在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

公开(公告)号：US5961629A

公开(公告)日：1999-10-05

申请号：US150706

申请日：1998-09-10

Applicant: Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

Inventor： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/28

CPC classification number: G06F9/3855 ,  G06F9/30054 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3885

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract translation: 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US5734584A

公开(公告)日：1998-03-31

申请号：US730658

申请日：1996-10-11

Applicant: Kevin R. Iadonato ,  Le Trong Nguyen

Inventor： Kevin R. Iadonato ,  Le Trong Nguyen

IPC: G06F5/00 ,  G06F7/00 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/40 ,  G06F15/00 ,  G06F15/76 ,  G06F17/00 ,  G06F17/50 ,  G06F19/00 ,  H01L21/82 ,  H01L27/00

CPC classification number: G06F9/30141 ,  G06F17/5068 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: A integrated structure layout for integrating Data Dependency Comparator (DDC) blocks, Tag Assignment Logic (TAL) blocks, and Register Port Multiplexer (RPM) blocks to conserve valuable semiconductor real estate. The DDC blocks are arranged in rows and columns. The TAL blocks are coupled to the DDC blocks to receive dependency information. The TAL blocks are positioned in one or more of the layout regions so as to be integrated with the DDC blocks to conserve area on the integrated circuit chip. The RPM blocks are coupled to the TAL blocks to receive tag information.

Abstract translation: 用于集成数据依赖比较器（DDC）块，标签分配逻辑（TAL）块和寄存器端口多路复用器（RPM）块的集成结构布局，以节省有价值的半导体空间。 DDC块以行和列排列。 TAL块耦合到DDC块以接收依赖信息。 TAL块位于一个或多个布局区域中，以便与DDC块集成以节省集成电路芯片上的面积。 RPM块被耦合到TAL块以​​接收标签信息。