A physical layer (PHY) device in an Ethernet type LAN is configured to permit ease of testing of the PHY device's logic. The PHY device comprises a PHY receiver, a start frame delimiter detector (SFD), and automatic checker circuitry in which the clock position and the PHY pop-up position of received signals can be determined. The automatic checker circuitry receives a data signal having a predetermined pattern corresponding to a valid data packet from a pattern generating circuit. The automatic checker circuitry outputs a verification signal indicating whether the supplied signals are valid. This arrangement supports a one pass test, which reduces production costs and testing duration.