公开(公告)号：US06836867B2

公开(公告)日：2004-12-28

申请号：US09950767

申请日：2001-09-13

申请人： Hirofumi Yonetoku

发明人： Hirofumi Yonetoku

IPC分类号： G01R3128

CPC分类号： G01R31/31813

摘要： A method of generating a pattern for testing a logic circuit includes judging whether generation of a test pattern is to be undertaken. If it is judged that generation of a test pattern is to be undertaken, a fault is selected for which the test pattern is to be generated. Generation is attempted of at least one test pattern necessary for detecting the selected fault. Fault simulation is carried out to find a test pattern, from among copies of the at least one test pattern, by which the most undetected faults are detected. If at least one test pattern is generated, the test pattern is re-activated.

摘要翻译： 产生用于测试逻辑电路的图案的方法包括：判断是否要进行测试图案的生成。 如果判定要进行测试图案的生成，则选择要产生测试图案的故障。 尝试生成检测所选故障所需的至少一个测试模式。 进行故障模拟，以从至少一个测试模式的副本中找到测试模式，通过该测试模式检测到最多未检测到的故障。 如果生成至少一个测试图案，则重新激活测试图案。

公开(公告)号：US06836866B2

公开(公告)日：2004-12-28

申请号：US10007391

申请日：2001-10-22

申请人： Jürgen Nolles ,  Gerd Dirscherl ,  Wolfgang Gärtner

发明人： Jürgen Nolles ,  Gerd Dirscherl ,  Wolfgang Gärtner

IPC分类号： G01R3128

CPC分类号： G01R31/3187 ,  G01R31/3025 ,  G01R31/31719 ,  G01R31/318555

摘要： A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.

摘要翻译： 电路包括内置自检，其中考虑到固定标准接口的使用，测试的逻辑电路的测试覆盖得到改善。 除了直接接口，复合电路还有一个附加的间接接口，将结构测试设备连接到功能电路。

公开(公告)号：US06834368B2

公开(公告)日：2004-12-21

申请号：US09960414

申请日：2001-09-24

申请人： Yasuyuki Nozuyama

发明人： Yasuyuki Nozuyama

IPC分类号： G01R3128

CPC分类号： G01R31/318591

摘要： This invention provides a semiconductor integrated circuit in which test facilitation technology (design for testability) of system on a chip (SOC) constructed of functional blocks or intellectual properties (IPs) is improved. This semiconductor integrated circuit takes out a test result of the functional block out of the SOC through a test result storage circuit which signature-compresses the test result.

摘要翻译： 本发明提供了一种半导体集成电路，其中改进了由功能块或知识产权（IP）构成的芯片上的系统（SOC）的测试便利化技术（可测试性设计）。 该半导体集成电路通过签名压缩测试结果的测试结果存储电路将功能块的测试结果从SOC中取出。

公开(公告)号：US06833722B2

公开(公告)日：2004-12-21

申请号：US09840815

申请日：2001-04-24

申请人： Cornelis Oene Cirkel ,  Yizi Xing

发明人： Cornelis Oene Cirkel ,  Yizi Xing

IPC分类号： G01R3128

CPC分类号： G01R31/2884 ,  G01R27/02

摘要： An electronic circuit device has contact terminal outside its package. The contact terminals are connected via the main current channels of two transistors connected in parallel between the contact terminals, so as to provide a switchable short circuit between the terminals. The device is tested by connecting two sense contacts of a resistance measuring device to the terminals and measuring the resistance between the sense contacts a first, second and third state respectively, the first and second transistor being switched on and off respectively in the first state and vice versa in the second state, both transistors being switched on in the third state. The resistance in the three states is modeled as a model resistance composed of a series resistance component in series with a first resistance component, a second resistance component and a parallel arrangement of said first and second resistance component respectively. The series resistance component is eliminate in tests of the device to avoid the effect of an unstable contact resistance between the terminals and the sense contacts.

摘要翻译： 电子电路装置在其封装外具有接触端子。 接触端子通过并联在接触端子之间的两个晶体管的主电流通道连接，以便在端子之间提供可切换的短路。 通过将电阻测量装置的两个感测触点连接到端子并分别在第一状态和第二状态之间分别测量感测触点之间的电阻，第一和第二晶体管分别导通和截止来测试该装置;以及 在第二状态中反之亦然，在第三状态下两个晶体管都导通。 三态中的电阻被建模为由分别与所述第一和第二电阻元件的第一电阻分量，第二电阻分量和并联布置串联电阻分量组成的模型电阻。 串联电阻分量在器件的测试中消除，以避免端子和感测触点之间的不稳定接触电阻的影响。

公开(公告)号：US06826721B2

公开(公告)日：2004-11-30

申请号：US10002017

申请日：2001-11-01

申请人： Eddie L. Williamson, Jr. ,  Kevin Lee Wible ,  Stephen P. Rozum

发明人： Eddie L. Williamson, Jr. ,  Kevin Lee Wible ,  Stephen P. Rozum

IPC分类号： G01R3128

CPC分类号： G01R31/31921

摘要： A data accelerator for use in a test vector sequencer includes a data translator, a plurality of sequence memory devices, and a switch. The data translator and the switch are configured via a control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to transfer a previously stored data segment. The test sequencer forwards a first application segment to a first memory device and acquires a subsequent application with a second memory device, detects a condition responsive to the completion of the segment acquisition and forwarding tasks, switches the roles of the first and second memory devices, and repeatedly switches and detects until all application segments have been processed.

摘要翻译： 用于测试矢量定序器的数据加速器包括数据转换器，多个序列存储器件和开关。 响应于第一序列存储器件准备好接收数据段并且准备第二序列存储器件准备传送先前存储的数据段的指示，经由控制信号来配置数据转换器和开关。 测试序列器将第一应用段转发到第一存储器设备并且利用第二存储器设备获取后续应用，检测响应于段获取和转发任务的完成的条件，切换第一和第二存储器设备的角色， 并重复切换和检测，直到所有应用程序段都被处理。

公开(公告)号：US06816992B2

公开(公告)日：2004-11-09

申请号：US09796342

申请日：2001-02-28

申请人： David H. Eby

发明人： David H. Eby

IPC分类号： G01R3128

CPC分类号： G01R31/318385 ,  G01R31/3183

摘要： A test set used for introducing a Poisson distribution of errors into a known digital data signal to produce a test signal uses an error signal generator that produces a Poisson distribution error signal. The error signal is then combined with the known digital data signal to produce a test signal with the Poisson distribution of errors. A pseudo-random binary sequence generator is used to produce a PRBS sequence and a comparator is used for comparing the PRBS sequence with a probability control signal. The comparator sets a single bit in the output stream of zeros when the PRBS sequence is less than the probability control signal. For multiple bit Poisson distribution error signals the PRBS generator and comparator combination may be replicated m times, or a single PRBS generator may be used and a unique independent subset of the PRBS sequence is applied to each of the multiple comparators.

摘要翻译： 用于将泊松分布的误差引入已知数字数据信号以产生测试信号的测试装置使用产生泊松分布误差信号的误差信号发生器。 然后将误差信号与已知的数字数据信号组合以产生具有泊松分布误差的测试信号。 伪随机二进制序列发生器用于产生PRBS序列，比较器用于比较PRBS序列与概率控制信号。 当PRBS序列小于概率控制信号时，比较器在零输出流中设置单个位。 对于多位泊松分布误差信号，可以将PRBS发生器和比较器组合复制m次，或者可以使用单个PRBS发生器，并且将PRBS序列的唯一独立子集应用于多个比较器中的每一个。

公开(公告)号：US06806731B2

公开(公告)日：2004-10-19

申请号：US10143880

申请日：2002-05-14

申请人： Ichiro Kohno

发明人： Ichiro Kohno

IPC分类号： G01R3128

CPC分类号： G01R31/318536 ,  G01R31/318541

摘要： A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.

摘要翻译： 一种半导体集成电路装置，其缩短了测试分割逻辑电路所需的时间以降低测试成本，并提供了故障检测方法。 逻辑电路被分为N个逻辑块，使用N + 1个扫描路径，包括扫描触发器，每个扫描触发器具有选择器，用于选择性地拾取被反馈到存储元件的存储元件的输出信号。 然后可以在这些逻辑块（逻辑1至逻辑N）上执行常见扫描操作，并且可以在逻辑块上连续执行测试操作。 本发明优选地消除了常规扫描操作中的重叠，导致较短的测试时间。

公开(公告)号：US06804801B2

公开(公告)日：2004-10-12

申请号：US09888025

申请日：2001-06-25

申请人： Barry Stanley Davies

发明人： Barry Stanley Davies

IPC分类号： G01R3128

CPC分类号： G01R31/31704

摘要： A system for fault insertion in an integrated circuit that resides in a functional portion of the integrated circuit. The fault insertion system is controlled through a Fault Control Register, comprising a Fault Identification Register (FIR), and a Fault Apply Register (FAR). The FIR is connected to a FIR decode block which, depending on the values contained in the FIR, applies signals to one or more node fault logic blocks. The node fault logic blocks either apply a test signal to a circuit node, or apply the normal system signals to the node. The FAR controls an enable signal to the FIR decode block, and determines when, and the duration, that the test signal will be applied. An External Control Bit of the FAR also allows manual control of the test signal.

摘要翻译： 一种集成电路中的故障插入系统，其驻留在集成电路的功能部分中。 故障插入系统由故障控制寄存器控制，包括故障识别寄存器（FIR）和故障应用寄存器（FAR）。 FIR连接到FIR解码块，其根据FIR中包含的值将信号应用于一个或多个节点故障逻辑块。 节点故障逻辑块将测试信号应用于电路节点，或将正常系统信号应用于节点。 FAR控制到FIR解码块的使能信号，并确定测试信号将被施加的时间和持续时间。 FAR的外部控制位也允许手动控制测试信号。

公开(公告)号：US06795945B2

公开(公告)日：2004-09-21

申请号：US09901377

申请日：2001-07-09

申请人： Volker Lueck

发明人： Volker Lueck

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： A method and an arrangement for testing digital circuits having at least one circuit logic and memory elements, which are interconnected to form at least one shift chain, in which test vectors are inserted into the shift chain and result vectors are retrieved from the shift chain. In at least one part of the shift chain, values from the memory elements are fed back to logic units, and the feedback values are combined with updated output values of the circuit logic in the logic units, and output values of the logic units are stored as internal test vectors in the memory elements in an internal test mode.

摘要翻译： 一种用于测试具有至少一个电路逻辑和存储器元件的数字电路的方法和装置，所述至少一个电路逻辑和存储器元件互连以形成至少一个移位链，其中将测试向量插入到所述换档链中并且从所述换档链中检索结果向量。 在移位链的至少一部分中，来自存储元件的值被反馈到逻辑单元，并且将反馈值与逻辑单元中的电路逻辑的更新的输出值组合，并且存储逻辑单元的输出值 作为内部测试向量的内存测试模式。

公开(公告)号：US06795943B2

公开(公告)日：2004-09-21

申请号：US09973894

申请日：2001-10-11

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

IPC分类号： G01R3128

CPC分类号： G11C29/14

摘要： A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

摘要翻译： 半导体存储器包括：第一解码器，根据第一至第四数据信号选择测试模式B的模式1-n中的任何一个;以及第二解码器，根据第五至第八数据信号选择测试模式B的模式1-n中的任何一个 。 当在测试模式A中未设置预定模式m + 1时，设置由第一和第二解码器选择的模式。 当设定了预定模式m + 1时，设置由第一解码器选择的模式。 因此，通过将四个数据输入/输出端子连接到测试器，可以在制造商侧设置测试模式B.