A new method is provided for the creation of metal plugs. After the gate electrode structures have been created on the surface of a semiconductor substrate, the Inter Level Dielectric (ILD) is deposited over the poly gates. The layer of ILD is polished, a second layer of dielectric is deposited over the layer of ILD. A stop layer is deposited over the second layer of dielectric, a Rapid Thermal Annealing (RTA) is performed to the stop layer and the thin layer of dielectric. The metal plugs are then patterned and deposited after which the process proceeds for the further creation of the interconnect metal.