公开(公告)号：US06830998B1

公开(公告)日：2004-12-14

申请号：US10462667

申请日：2003-06-17

申请人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L213205

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

摘要翻译： 在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。 实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

公开(公告)号：US06830996B2

公开(公告)日：2004-12-14

申请号：US10395345

申请日：2003-03-24

申请人： Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen

发明人： Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L213205

CPC分类号： H01L21/28202 ,  H01L21/02052 ,  H01L21/321 ,  H01L29/518

摘要： The present disclosure provides a method is provided for fabricating a metal oxide semiconductor (MOS) gate stack on a semiconductor substrate. The method includes generating moisture on a surface of the semiconductor substrate to form an oxide layer less than 10 nanometers thin and performing a nitridation process on the thin oxide layer. After the nitridation process, the method includes performing a polysilicon deposition process on the surface of the semiconductor substrate, doping the polysilicon deposition to a level of 5×1015 at/cm3, and cleaning the doped polysilicon with a light ammonia solution.

摘要翻译： 本公开提供了一种用于在半导体衬底上制造金属氧化物半导体（MOS）栅极堆叠的方法。 该方法包括在半导体衬底的表面上产生湿气以形成小于10纳米薄的氧化物层，并对薄氧化物层进行氮化处理。 在氮化处理之后，该方法包括在半导体衬底的表面上执行多晶硅沉积工艺，将多晶硅沉积掺杂至5×10 15 at / cm 3的水平，并用轻氨溶液清洗掺杂的多晶硅。

公开(公告)号：US06825106B1

公开(公告)日：2004-11-30

申请号：US10676987

申请日：2003-09-30

申请人： Wei Gao ,  Yoshi Ono

发明人： Wei Gao ,  Yoshi Ono

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/78

摘要： A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided in the sputtering chamber. The sputtering power and oxygen partial pressure within the chamber is set to deposit a film comprising niobium monoxide, without excess amounts of elemental niobium, NbO2 insulator, or Nb2O5 insulator. The deposition method may be incorporated into a standard CMOS fabrication process, or a replacement gate CMOS process.

摘要翻译： 提供了一种沉积一氧化monoxide栅的方法。 在溅射室内设置元素金属靶或复合铌靶。 在溅射室中提供具有栅极电介质的衬底，例如二氧化硅或高k栅极电介质。 室内的溅射功率和氧分压被设定为沉积包含一氧化铌的膜，而不含过量的元素铌，NbO 2绝缘体或Nb 2 O 5绝缘体。 沉积方法可以结合到标准CMOS制造工艺或替代栅极CMOS工艺中。

公开(公告)号：US06809017B2

公开(公告)日：2004-10-26

申请号：US10452088

申请日：2003-05-30

申请人： Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

发明人： Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

IPC分类号： H01L213205

CPC分类号： H01L21/28176 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4925 ,  H01L29/517

摘要： Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

摘要翻译： 制造半导体器件的方法 半导体器件包括衬底，形成在衬底上的高k栅介质层和沉积在高k栅介质层上的无氢栅电极，其中无氢栅电极是导电的。 该方法包括在衬底上沉积高k栅极电介质层，在栅极电介质层上溅射栅电极并处理栅电极使得栅电极是导电的。

公开(公告)号：US06797601B2

公开(公告)日：2004-09-28

申请号：US09332271

申请日：1999-06-11

申请人： Klaus Florian Schuegraf ,  Randhir P. S. Thakur

发明人： Klaus Florian Schuegraf ,  Randhir P. S. Thakur

IPC分类号： H01L213205

CPC分类号： H01L21/3215 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28273 ,  H01L21/76889 ,  H01L27/115

摘要： The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

摘要翻译： 本发明包括堆叠的半导体器件，包括栅极堆叠，字线，PROM，导电互连线以及用于形成这种结构的方法。 一方面，本发明包括形成导线的方法，包括：a）形成多晶硅层; 形成针对多晶硅层的硅化物层; b）在硅化物层内提供电导率增强杂质; 以及c）将所述多晶硅层和所述硅化物层设置成导线形状。 在另一方面，本发明包括可编程只读存储器件，其包括：a）衬底上的第一介电层; b）在第一介电层上的浮栅; c）浮置栅极上的第二电介质层; d）在第二介电层上的导电线; 以及e）所述导电线上的金属硅化物层，所述金属硅化物层包含III族掺杂剂或V族掺杂剂。

公开(公告)号：US06790754B2

公开(公告)日：2004-09-14

申请号：US10747595

申请日：2003-12-29

申请人： Cheolsoo Park

发明人： Cheolsoo Park

IPC分类号： H01L213205

CPC分类号： H01L29/66583 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/78

摘要： Method for forming contact electrodes in a semiconductor device are disclosed. An example method comprises sequentially forming a pad oxide layer, a pad nitrate layer, a dummy oxide layer, and a capping nitride layer on a substrate. These layers and the substrate are then patterned to form a trench. The trench us filled with an insulating material to form a device isolation stripe. The resulting structure is then patterned to form a trench. Spacers are formed on the sidewalls of the trench and ions are implanted into the substrate beneath the trench to form local channel portions. A gate insulating layer and a gate electrode are then formed by deposition. Thereafter, the dummy oxide layer and the capping nitride layer are removed and source/drain portions are defined. Contact electrodes are then formed by deposition of a metal layer.

摘要翻译： 公开了在半导体器件中形成接触电极的方法。 示例性方法包括在衬底上依次形成衬垫氧化物层，衬垫硝酸盐层，虚拟氧化物层和覆盖氮化物层。 然后将这些层和衬底图案化以形成沟槽。 沟槽我们填充绝缘材料以形成器件隔离条纹。 然后将所得结构图案化以形成沟槽。 间隔件形成在沟槽的侧壁上，并且离子被注入到沟槽下方的衬底中以形成本地通道部分。 然后通过沉积形成栅极绝缘层和栅电极。 此后，去除虚拟氧化物层和覆盖氮化物层，并限定源极/漏极部分。 然后通过沉积金属层形成接触电极。

公开(公告)号：US06770550B2

公开(公告)日：2004-08-03

申请号：US09441889

申请日：1999-11-17

申请人： Tatsuya Kunikiyo

发明人： Tatsuya Kunikiyo

IPC分类号： H01L213205

CPC分类号： H01L21/28202 ,  H01L21/26506 ,  H01L21/28088 ,  H01L23/544 ,  H01L29/1033 ,  H01L29/4941 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： After a channel layer (7) containing nitrogen is formed in a channel region (5) in the main surface of a semiconductor substrate (1), a gate insulating film (9) and insulating films (10) are formed as oxide film by a thermal oxidation on the main surface of the semiconductor substrate (1). The insulating films (10) are thicker than the gate insulating film (9) because the oxidation reaction is suppressed in the nitrogen-introduced region. Further, stresses caused by the oxidation are suppressed-around the connections between the gate insulating film (9) and the insulating films (10). Accordingly, reduction in leakage current and improvement of gate insulating film reliability are compatibly realized.

摘要翻译： 在半导体衬底（1）的主表面中的通道区域（5）中形成含有氮的沟道层（7）之后，通过栅极绝缘膜（9）和绝缘膜（10）形成氧化膜 在半导体衬底（1）的主表面上的热氧化。 绝缘膜（10）比栅极绝缘膜（9）厚，因为在氮导入区域抑制了氧化反应。 此外，围绕栅极绝缘膜（9）和绝缘膜（10）之间的连接，抑制由氧化引起的应力。 因此，能够兼容地实现漏电流的降低和栅绝缘膜的可靠性的提高。

公开(公告)号：US06764932B2

公开(公告)日：2004-07-20

申请号：US10056607

申请日：2002-01-24

申请人： Hua-Shuang Kong ,  John Adam Edmond ,  Kevin Ward Haberern ,  David Todd Emerson

发明人： Hua-Shuang Kong ,  John Adam Edmond ,  Kevin Ward Haberern ,  David Todd Emerson

IPC分类号： H01L213205

CPC分类号： H01L21/0237 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01S5/3202 ,  H01S2304/12

摘要： A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion. The gallium nitride layer is then grown laterally by pendeoepitaxy over the trenches.

摘要翻译： 在衬底上制造氮化镓基半导体结构的方法包括以下步骤：在衬底上直接形成具有至少一个开口的掩模，通过该开口生长缓冲层，并从其中向上生长一层氮化镓 缓冲层和横向穿过掩模。 在从掩模生长氮化镓期间，氮化镓层的垂直和水平生长速率保持在足以防止在所述掩模上成核的多晶材料中断氮化镓层的横向生长的速率。 在替代实施例中，该方法包括形成限定衬底中相邻沟槽的至少一个凸起部分，并在衬底上形成掩模，该掩模在凸起部分的上表面上具有至少一个开口。 缓冲层可以从凸起部分的上表面生长。 然后氮化镓层通过在沟槽上的外延生长而横向生长。

公开(公告)号：US06762114B1

公开(公告)日：2004-07-13

申请号：US10335557

申请日：2002-12-31

申请人： James Joseph Chambers

发明人： James Joseph Chambers

IPC分类号： H01L213205

CPC分类号： H01L29/513 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.

摘要翻译： 公开了用于制造晶体管栅极结构的方法，其中通过在衬底或任何有意界面层上形成成核促进层来降低高k介电层粗糙度，并且在成核促进层上形成高k栅极电介质。 成核促进层的厚度为10μm以下，例如单层或亚单层，其包含金属，金属硅化物或金属硅酸盐，其促进高k栅极电介质材料的均匀化学气相沉积 增加基底或有意界面层上的成核位点的密度。

公开(公告)号：US06734089B1

公开(公告)日：2004-05-11

申请号：US10345542

申请日：2003-01-16

申请人： Yongjun Jeff Hu ,  Satish Bedge ,  Kevin Torek

发明人： Yongjun Jeff Hu ,  Satish Bedge ,  Kevin Torek

IPC分类号： H01L213205

CPC分类号： H01L27/10891 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L27/11

摘要： Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the process flow to remove or weaken certain layers formed in the wordlines. For instance, an SiNx layer and a crystallized W2N layer may form during the fabrication of the wordline. While the layers may provide certain advantages at certain points in the fabrication process, they may be undesirable at subsequent points. One or more anneal processes may be implemented at various points in the processing to eliminate the crystallized W2N layer and weaken the SiNx layer.

摘要翻译： 制造半导体器件的制造技术。 更具体地，提供了用于在存储器件中制造字线的技术。 可以将比热处理添加到工艺流程中以去除或削弱在字线中形成的某些层。 例如，在制作字线期间可能形成SiNx层和结晶化的W2N层。 虽然这些层可以在制造过程的某些点提供某些优点，但是它们在随后的点处可能是不期望的。 可以在处理的各个点处实施一个或多个退火工艺，以消除结晶的W2N层并削弱SiNx层。