- 专利标题: Method of manufacturing semiconductor device
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申请号: US09206561申请日: 1998-12-08
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公开(公告)号: US06271070B1公开(公告)日: 2001-08-07
- 发明人: Naoki Kotani , Keiichiro Shimizu
- 申请人: Naoki Kotani , Keiichiro Shimizu
- 优先权: JP9-356693 19971225; JP9-356700 19971225
- 主分类号: H01L218238
- IPC分类号: H01L218238
摘要:
On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.
公开/授权文献
- US20010003660A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 公开/授权日:2001-06-14
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