公开(公告)号：US06271070B1

公开(公告)日：2001-08-07

申请号：US09206561

申请日：1998-12-08

申请人： Naoki Kotani ,  Keiichiro Shimizu

发明人： Naoki Kotani ,  Keiichiro Shimizu

IPC分类号： H01L218238

摘要： On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

公开(公告)号：US08125608B2

公开(公告)日：2012-02-28

申请号：US12296905

申请日：2007-02-09

申请人： Naoki Kotani ,  Kimio Takahashi

发明人： Naoki Kotani ,  Kimio Takahashi

IPC分类号： G02F1/1333 ,  G02F1/1339

CPC分类号： G02F1/133711 ,  G02F1/1339 ,  G02F1/1341 ,  G02F2001/133354

摘要： A substrate for a display having, on a surface thereof, a sealing compound disposed along a periphery of the substrate spaced at a predetermined interval from an outer edge of a display part to which an oriented film is applied; and a convex portion or/and a concave portion, for preventing the applied oriented film from spreading to the sealing compound, provided between the sealing compound and the outer edge of the display part. The convex portion has a configuration of a bank continuous or uncontinuous, whereas the concave portion is formed as a plurality of independent portions arranged side by side or dotted between the outer edge of the display part and the sealing compound.

摘要翻译： 一种用于显示器的基板，其表面上具有沿着与从其被施加定向膜的显示部分的外边缘以预定间隔间隔开的沿着基板周边设置的密封化合物; 以及设置在密封化合物和显示部的外缘之间的用于防止所施加的取向膜扩散到密封化合物的凸部或/和凹部。 凸部具有连续或不连续的堤的构造，而凹部形成为在显示部分的外边缘和密封化合物之间并排布置或点划线的多个独立部分。

公开(公告)号：US07829956B2

公开(公告)日：2010-11-09

申请号：US11518169

申请日：2006-09-11

申请人： Naoki Kotani

发明人： Naoki Kotani

IPC分类号： H01L27/092

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L29/7833 ,  H01L29/7843 ,  Y10S257/903

摘要： Both a compressive-stress-applying insulating film and a tensile-stress-applying insulating film cover an N-type MIS transistor formed at an SRAM access region of a semiconductor substrate. On the other hand, a tensile-stress-applying insulating film covers an N-type MIS transistor formed at an SRAM drive region of the semiconductor substrate.

摘要翻译： 压应力施加绝缘膜和拉伸应力施加绝缘膜都覆盖形成在半导体基板的SRAM访问区域的N型MIS晶体管。 另一方面，拉伸应力施加绝缘膜覆盖形成在半导体基板的SRAM驱动区域的N型MIS晶体管。

公开(公告)号：US07808049B2

公开(公告)日：2010-10-05

申请号：US11491259

申请日：2006-07-24

申请人： Naoki Kotani

发明人： Naoki Kotani

IPC分类号： H01L29/76

CPC分类号： H01L27/11

摘要： In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.

摘要翻译： 在半导体器件中，N型逻辑区域NL中的晶体管被​​拉伸应力施加膜覆盖，P型逻辑区域PL中的晶体管被​​压缩应力膜覆盖。 P型SRAM区域PS和N型SRAM区域NS中的晶体管覆盖有比由上述两个膜施加的应力低的应力的绝缘膜。

公开(公告)号：US07538397B2

公开(公告)日：2009-05-26

申请号：US11186785

申请日：2005-07-22

申请人： Naoki Kotani

发明人： Naoki Kotani

IPC分类号： H01L27/04

CPC分类号： H01L21/823443 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/0629

摘要： A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so that variations in a resistance value of a resistor are suppressed. Also, the gate electrodes of the MIS transistors and the like are exposed when thermal treatment for activating an impurity, and therefore breakdown of respective gate insulation films of the MIS transistors hardly occurs.

摘要翻译： 半导体器件包括由氧化硅膜覆盖的电阻元件。 在半导体器件中，对于MIS晶体管和杂质掺杂层的相应栅电极，即非硅化物区域暴露，进行用于激活杂质的热处理和硅化。 因此，抑制了杂质的自掺杂，从而抑制了电阻器的电阻值的变化。 此外，当用于激活杂质的热处理时，MIS晶体管等的栅极电极暴露，因此几乎不发生MIS晶体管的各个栅极绝缘膜的击穿。

公开(公告)号：US20070080405A1

公开(公告)日：2007-04-12

申请号：US11542269

申请日：2006-10-04

申请人： Naoki Kotani ,  Gen Okazaki ,  Shinji Takeoka ,  Junji Hirase ,  Akio Sebe ,  Kazuhiko Aida

发明人： Naoki Kotani ,  Gen Okazaki ,  Shinji Takeoka ,  Junji Hirase ,  Akio Sebe ,  Kazuhiko Aida

IPC分类号： H01L29/94

CPC分类号： H01L21/28097 ,  H01L21/28123 ,  H01L29/4975 ,  H01L29/66545

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由半导体衬底中的隔离区围绕的有源区; 形成在有源区上的栅极绝缘膜; 以及形成在有源区域和邻近有源区域的隔离区域之间的边界上的栅电极。 栅电极包括位于有源区上方的第一部分，栅极绝缘膜插入其间，并且在厚度方向上完全由硅化物制成，而第二部分位于隔离区上方，并由硅区域 以及覆盖硅区域的硅化物区域。

公开(公告)号：US20070045695A1

公开(公告)日：2007-03-01

申请号：US11491936

申请日：2006-07-25

申请人： Shinji Takeoka ,  Akio Sebe ,  Junji Hirase ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida

发明人： Shinji Takeoka ,  Akio Sebe ,  Junji Hirase ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida

IPC分类号： H01L29/94

CPC分类号： H01L21/82345 ,  H01L21/28097 ,  H01L21/3212 ,  H01L21/823443 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

摘要： A Ni film is deposited over the entire surface of a substrate including a silicon gate. Then, the silicon gate is partially removed by, for example, CMP, thereby leaving a Ni layer having a flat upper surface and a uniform thickness directly on the silicon gate. Subsequently, silicidation is performed, thereby forming a gate electrode having a uniform silicide phase.

摘要翻译： 在包括硅栅极的衬底的整个表面上沉积Ni膜。 然后，通过例如CMP部分去除硅栅极，由此在硅栅极上直接留下具有平坦的上表面和均匀厚度的Ni层。 随后，进行硅化，从而形成具有均匀硅化物相的栅电极。

公开(公告)号：US20070040199A1

公开(公告)日：2007-02-22

申请号：US11491231

申请日：2006-07-24

申请人： Naoki Kotani

发明人： Naoki Kotani

IPC分类号： H01L29/94

CPC分类号： H01L27/11 ,  H01L27/1116

摘要： In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with a layered film including a tensile stress applying film and a compressive stress applying film.

摘要翻译： 在半导体器件中，N型逻辑区域NL中的晶体管被​​拉伸应力施加膜覆盖，P型逻辑区域PL中的晶体管被​​压缩应力膜覆盖。 P型SRAM区域PS和N型SRAM区域NS中的晶体管被​​包括拉伸应力施加膜和压应力施加膜的层状膜覆盖。

公开(公告)号：US07053450B2

公开(公告)日：2006-05-30

申请号：US10834112

申请日：2004-04-29

申请人： Naoki Kotani

发明人： Naoki Kotani

IPC分类号： H01L29/78

CPC分类号： H01L29/1045 ,  H01L21/823807 ,  H01L21/823814

摘要： A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate electrode, lightly doped diffusion layers provided in the respective regions of the substrate located below the edge portions of the gate electrodes, heavily doped diffusion layers provided in the respective regions of the substrate located laterally below the gate electrode and the sidewalls, and pocket diffusion layers covering the lower portions of the lightly doped diffusion layers and parts of the side surfaces thereof in overlapping relation with each other below the gate electrode. Impurity concentrations in the pocket diffusion layers are set such that the threshold of the MISFET has a desired value.

摘要翻译： 半导体器件中的MISFET具有设置在基板上的栅极绝缘膜，设置在栅极绝缘膜上的栅电极，设置在栅电极的侧面的侧壁，设置在基板的各个区域中的轻掺杂扩散层 在栅电极的边缘部分的下方，设置在位于栅电极和侧壁的下方的衬底的相应区域中的重掺杂扩散层以及覆盖轻掺杂扩散层的下部和侧面部分的凹穴扩散层 其表面在栅电极下方彼此重叠关系。 设置袋扩散层中的杂质浓度使得MISFET的阈值具有期望值。

公开(公告)号：US08264045B2

公开(公告)日：2012-09-11

申请号：US12886036

申请日：2010-09-20

申请人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

发明人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

摘要翻译： 包括SRAM部分和逻辑电路部分的半导体器件包括：第一n型MIS晶体管，包括第一n型栅极，其形成有插入在SRAM中的半导体衬底的第一元件形成区域上的第一栅极绝缘膜 部分; 以及第二n型MIS晶体管，其包括形成有第二栅极绝缘膜的第二n型栅电极，所述第二栅极绝缘膜插入在所述逻辑电路部分中的所述半导体衬底的第二元件形成区域上。 第一n型栅电极中的第一n型杂质的第一杂质浓度低于第二n型栅极中的第二n型杂质的第二杂质浓度。