Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

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US06271125B1 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure 有权

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专利标题： Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure
申请号： US09713799

申请日： 2000-11-16
公开(公告)号： US06271125B1

公开(公告)日： 2001-08-07
发明人: Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
申请人： Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
主分类号： H01L214763
IPC分类号： H01L214763

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

摘要：

A method for reducing the high aspect ratios, encountered when forming, and filling, narrow diameter contact holes, in thick insulator layers, has been developed, featuring a two step contact hole opening and filling procedure. First, lower narrow diameter contact holes are opened in lower levels of insulator layers, then filled with tungsten. After deposition of upper levels of insulator layers, upper narrow diameter contact holes are formed, exposing the tungsten filled, lower diameter contact holes. A second tungsten layer fills the upper, narrow diameter contact hole, resulting in a final narrow diameter contact hole, in thick insulator layers, formed with reduced aspect ratios, via use of the two contact hole openings, and the two tungsten fill procedures. In addition these procedures allow a damascene, tungsten bit line structure, to be formed in a dual shaped opening, in lower insulator layers.

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