发明授权
US06272620B1 Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
失效
中央处理单元具有32位长度的指令队列，在一个指令提取操作中获取16位固定长度的两个指令
- 专利标题： Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
- 专利标题（中）： 中央处理单元具有32位长度的指令队列，在一个指令提取操作中获取16位固定长度的两个指令
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申请号： US09543387申请日： 2000-04-04
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公开(公告)号： US06272620B1公开(公告)日： 2001-08-07
- 发明人: Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
- 申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
- 优先权： JP3-178739 19910624; JP4-154525 19920521
- 主分类号： G06F1500
- IPC分类号： G06F1500
摘要：
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
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