公开(公告)号：US20090157953A1

公开(公告)日：2009-06-18

申请号：US12320679

申请日：2009-02-02

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US20080313444A1

公开(公告)日：2008-12-18

申请号：US12195856

申请日：2008-08-21

申请人： Shumpei KAWASAKI ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei KAWASAKI ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F9/06

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US07363466B2

公开(公告)日：2008-04-22

申请号：US11354622

申请日：2006-02-14

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

摘要翻译： 内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 由此，CPU核心2可以将来自内置存储器的两个数据值同时传送到DSP引擎3。 此外，第三总线XAB和XDB以及第二总线YAB和YDB也与要外部接口的第一总线IAB和IDB分开，并且CPU核心2可以与访问第二存储器4和6并行地访问外部存储器 和第一存储器5和7。

公开(公告)号：US06999350B2

公开(公告)日：2006-02-14

申请号：US10898333

申请日：2004-07-26

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US06889240B2

公开(公告)日：2005-05-03

申请号：US10694771

申请日：2003-10-29

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/302 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F15/78 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加 防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

公开(公告)号：US06690603B2

公开(公告)日：2004-02-10

申请号：US10158901

申请日：2002-06-03

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US06335879B1

公开(公告)日：2002-01-01

申请号：US09705835

申请日：2000-11-06

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1400

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有和电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储单元的可重写非易失性存储器，并且被设置为便于闪速擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US06181598B2

公开(公告)日：2001-01-30

申请号：US09435037

申请日：1999-11-05

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有和电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储单元的可重写非易失性存储器，并且被设置为便于闪速擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US5581503A

公开(公告)日：1996-12-03

申请号：US520721

申请日：1995-07-31

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F9/445 ,  G06F15/78 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11526 ,  G06F15/7814 ,  G06F15/7821 ,  G06F9/445 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C7/1045 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/105 ,  Y02B60/185

摘要： An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a CPU and the above-mentioned electrically rewritable flash memory formed in a single semiconductor chip includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the CPU and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 一种电可重写闪速存储器件，其具有以存储单元的行和列布置的存储单元阵列，并且被分成具有不同存储容量的多个存储块。 每个存储器块具有一行或多行存储器单元。 为每个存储块提供公共电压控制电路，用于将第一电位施加到用于存储块的公共导体，该存储块包含用施加到其相关联的数据线导体的写入操作和第二电位的选择电压选择的存储器单元 高于用于存储块的公共导体的第一电位，该存储块包含未选择施加到其相关联的数据线导体的选择电压并且不包含用于写入操作的选定存储器单元的存储器单元。 具有CPU和上述形成在单个半导体芯片中的电可重写闪存的微型计算机包括：输入端子，用于接收用于在微控制器的控制下在闪速存储器被重写的第一操作模式之间切换微型计算机的操作模式信号 CPU和第二操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US5321845A

公开(公告)日：1994-06-14

申请号：US94920

申请日：1993-07-22

申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

CPC分类号： G06F9/24 ,  G06F15/7814

摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。