发明授权
- 专利标题: Semiconductor integrated circuit
- 专利标题(中): 半导体集成电路
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申请号: US09532734申请日: 2000-03-22
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公开(公告)号: US06278628B1公开(公告)日: 2001-08-21
- 发明人: Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
- 申请人: Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
- 优先权: JP11-085386 19990329
- 主分类号: G11C506
- IPC分类号: G11C506
摘要:
In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.
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