发明授权
- 专利标题: Fault resilient/fault tolerant computing
- 专利标题(中): 故障恢复/容错计算
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申请号: US09190269申请日: 1998-11-13
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公开(公告)号: US06279119B1公开(公告)日: 2001-08-21
- 发明人: Thomas D. Bissett , Paul A. Leveille , Erik Muench
- 申请人: Thomas D. Bissett , Paul A. Leveille , Erik Muench
- 主分类号: G06F1100
- IPC分类号: G06F1100
摘要:
A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.
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