Invention Grant
US06281738B1 Bus driver, output adjusting method and driver 失效
总线驱动器,输出调节方式及驱动

  • Patent Title: Bus driver, output adjusting method and driver
  • Patent Title (中): 总线驱动器,输出调节方式及驱动
  • Application No.: US09387510
    Application Date: 1999-09-01
  • Publication No.: US06281738B1
    Publication Date: 2001-08-28
  • Inventor: Hiroshi Kamiya
  • Applicant: Hiroshi Kamiya
  • Priority: JP10-250266 19980904
  • Main IPC: H01L3500
  • IPC: H01L3500
Bus driver, output adjusting method and driver
Abstract:
A bus driver circuit includes a diode, a resistor, a constant voltage source, a constant voltage comparing circuit, the first output buffer circuit, the second output buffer circuit. An anode of the diode is connected to a power source, whereas a cathode thereof is connected to an end of the resistor. The other end of the resistor is connected to the ground. The constant voltage source applies, to the voltage comparing circuit, a reference voltage, which is substantially identical with a voltage of the cathode included in the diode when a temperature of the first output buffer circuit becomes a temperature Tcr at which a ringing event occurs in an output signal from the bus driver circuit. The voltage comparing circuit compares the reference voltage and the voltage of the cathode. The voltage comparing circuit outputs a control signal to the first output buffer circuit in accordance with the compared result. Both of the first and second output buffer circuits are connected to a signal output terminal to be connected to a bus and a signal input terminal connected to a signal processor. The first output buffer circuit is a three state buffer circuit. While the bus driver circuit is being operated, the voltage comparing circuit compares the voltage of the cathode and the reference voltage. When the voltage of the cathode is equal to or above the reference voltage, that is, when the temperature of the first output buffer circuit becomes equal to or above the temperature Tcr, the voltage comparing circuit outputs, to the first output buffer circuit, a control signal for inactivating the first output buffer circuit. The first output buffer circuit is inactivated when the control signal is input thereto.
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