公开(公告)号：US08593003B2

公开(公告)日：2013-11-26

申请号：US13159723

申请日：2011-06-14

申请人： Tomoaki Niwa ,  Hiroshi Kamiya ,  Yoshinobu Nakano

发明人： Tomoaki Niwa ,  Hiroshi Kamiya ,  Yoshinobu Nakano

IPC分类号： B60L1/02

CPC分类号： F02B77/11 ,  F02B63/04

摘要： An outdoor power generating apparatus includes a housing placed at an outside and including a power generation chamber, a power generation source accommodated in the power generation chamber and formed by either one of an engine and a fuel cell, an intake portion provided within the housing and positioned at an upper side of the power generation source, the intake portion including an outside air inlet portion that opens to a side wall of the housing to bring an outside air, the intake portion including a meander passage that connects the outside air inlet portion to the power generation chamber while bringing the outside air to meander from the outside air inlet portion towards the power generation chamber, and a drain port provided at the meander passage and discharging a water in a liquid state that remains at the meander passage to an outside of the meander passage.

摘要翻译： 室外发电装置包括：外壳，其外部设置有发电室，容纳在发电室中的发电源，由发动机和燃料电池中的任一个形成，设置在壳体内的进气部， 位于所述发电源的上侧，所述进气部包括通向所述壳体的侧壁的外部空气入口部，以使外部空气进入，所述进气部包括将所述外部空气入口部连接到所述外部空气入口部的曲折通路 发电室，同时使外部空气从外部空气入口部分朝向发电室弯曲;以及排出口，设置在曲折通道处，并将残留在曲折通道的液体状态的水排出到外部， 曲折通道。

公开(公告)号：US20100066971A1

公开(公告)日：2010-03-18

申请号：US12559587

申请日：2009-09-15

申请人： HIROSHI KAMIYA

发明人： HIROSHI KAMIYA

IPC分类号： G02C7/12

CPC分类号： G02C7/12 ,  A61B5/01 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/0476 ,  A61B5/0816 ,  A61B5/16 ,  A61B5/165 ,  A61B5/4261 ,  G02C7/10

摘要： An adjustment device adapted to glasses each including two polarization filters having adjustable transmission axes varying an angle therebetween in a front view is constituted of a physical parameter receiving unit for receiving at least one physical parameter which is produced by measuring the user's body, an angle calculation unit for calculating a target angle to be formed between the transmission axes of the polarization filters based on the received physical parameter, and a polarization filter adjustment unit for rotating at least one of the polarization filters, thus making the present angle formed between the transmission axes of the polarization filters agree with the target angle. Thus, it is possible to reduce a load or strain imparted to a user's eyes in light of the user's fatigued condition.

摘要翻译： 一种调整装置，其适于在前视图中包括具有在其间改变角度的可调透镜轴的两个偏振滤光器的眼镜由物理参数接收单元构成，该物理参数接收单元用于接收通过测量用户身体产生的至少一个物理参数，角度计算 用于基于所接收的物理参数来计算在所述偏振滤光器的透射轴之间形成的目标角的单元，以及用于旋转所述偏振滤光器中的至少一个的偏振滤光器调节单元，从而使得形成在所述透射轴之间的所述当前角度 的偏振滤光片与目标角度一致。 因此，可以根据使用者的疲劳状况来减轻施加给用户的眼睛的负荷或应变。

公开(公告)号：US07514956B2

公开(公告)日：2009-04-07

申请号：US11699358

申请日：2007-01-30

申请人： Yasushi Nobutaka ,  Hiroshi Kamiya ,  Kunio Ohno

发明人： Yasushi Nobutaka ,  Hiroshi Kamiya ,  Kunio Ohno

IPC分类号： H03K17/16

CPC分类号： H04B3/00

摘要： A first and a second charging circuit each having a diode and a capacitor are connected to a buffer. In the first charging circuit, an overshoot based on a reflected signal generated by an output signal is stored as an electric charge to the capacitor, and in the second charging circuit, an undershoot based on a reflected signal generated by an input signal is charged as an electric charge to the capacitor, whereby the energy of the overshoot and the like is recovered. These charges are collected in the charging circuit, stored in the capacitor, converted into a power supply voltage of an internal power supply by a stabilization circuit, and are supplied as an internal power supply. The reflected energy of the signal generated during signal transmission at the time of data transfer between semiconductor devices is stored, and the stored energy is used in driving the signals.

摘要翻译： 每个具有二极管和电容器的第一和第二充电电路连接到缓冲器。 在第一充电电路中，基于由输出信号产生的反射信号的过冲作为电荷被存储到电容器，并且在第二充电电路中，基于由输入信号产生的反射信号的下冲被充电为 电容器的电荷，从而恢复过冲等的能量。 这些电荷被收集在充电电路中，存储在电容器中，由稳定电路转换为内部电源的电源电压，并作为内部电源供给。 存储在半导体器件之间的数据传输时在信号传输期间产生的信号的反射能量，并且将存储的能量用于驱动信号。

公开(公告)号：US20080157722A1

公开(公告)日：2008-07-03

申请号：US11947868

申请日：2007-11-30

申请人： Yasushi NOBUTAKA ,  Hiroshi Kamiya ,  Masakazu Hayashi ,  Masaaki Konno ,  Wenbeen Yao

发明人： Yasushi NOBUTAKA ,  Hiroshi Kamiya ,  Masakazu Hayashi ,  Masaaki Konno ,  Wenbeen Yao

IPC分类号： H02J7/00

CPC分类号： H02J7/0047 ,  H01M10/44 ,  H02J2007/0098

摘要： In a battery exchange system for facilitating exchange at appropriate intervals of a chargeable battery with another fully charged chargeable battery for charging, a user device having characteristic identification information reads a serial number from a battery when the battery is installed and transmits to a control device correspondence information in which the identification information and the serial number have been placed in correspondence with each other. A charging device reads the serial number from a battery when charging of the battery has been completed and transmits the serial number to the control device. The control device calculates a scheduled charging time of the battery having the serial number that has been transmitted from the charging device based on the time of reception of the correspondence information that was transmitted from user device and, before the calculated scheduled charging time, carries out notification prompting battery exchange.

摘要翻译： 在电池更换系统中，为了便于在可充电电池的适当间隔与另一个完全充电的可充电电池进行充电交换，具有特征识别信息的用户装置在电池安装时从电池读取序列号并发送到控制装置的对应 已经将识别信息和序列号相对应地放置的信息。 充电装置在电池充电完成时从电池读取序列号并将序列号发送到控制装置。 控制装置基于从用户装置发送的对应信息的接收时间，计算从充电装置发送的序列号的电池的预定充电时间，并且在计算出的预定充电时间之前执行 通知提示电池更换。

公开(公告)号：US06531901B2

公开(公告)日：2003-03-11

申请号：US09814982

申请日：2001-03-23

申请人： Hiroshi Kamiya

发明人： Hiroshi Kamiya

IPC分类号： H03B100

CPC分类号： G06F13/4077

摘要： A high-speed bus includes a bus line to be connected with a bus driver and a bus receiver. Pull-up resistors are connected to both ends of the bus line for feeding a given pull-up electric potential thereto. A series resistor is further connected between the bus line and each of the bus driver and the bus receiver. The bus driver includes a series resistor and a capacitive component which are connected in series between the bus line and the ground. The bus receiver includes a waveform shaping component connected to the bus line for shaping a waveform of an inputted signal, and a receiver circuit receiving as an input thereof an output of the waveform shaping component.

摘要翻译： 高速总线包括与总线驱动器和总线接收器连接的总线。 上拉电阻连接到总线的两端，用于给定给定的上拉电位。 总线线路和总线驱动器和总线接收器之间还连接有串联电阻器。 总线驱动器包括串联电阻器和电容元件，串联连接在总线和地之间。 总线接收器包括连接到总线的波形整形部件，用于整形输入信号的波形，以及接收器电路作为其输入端接收波形整形部件的输出。

公开(公告)号：US06281738B1

公开(公告)日：2001-08-28

申请号：US09387510

申请日：1999-09-01

申请人： Hiroshi Kamiya

发明人： Hiroshi Kamiya

IPC分类号： H01L3500

CPC分类号： H03K19/00369 ,  H03K19/00346

摘要： A bus driver circuit includes a diode, a resistor, a constant voltage source, a constant voltage comparing circuit, the first output buffer circuit, the second output buffer circuit. An anode of the diode is connected to a power source, whereas a cathode thereof is connected to an end of the resistor. The other end of the resistor is connected to the ground. The constant voltage source applies, to the voltage comparing circuit, a reference voltage, which is substantially identical with a voltage of the cathode included in the diode when a temperature of the first output buffer circuit becomes a temperature Tcr at which a ringing event occurs in an output signal from the bus driver circuit. The voltage comparing circuit compares the reference voltage and the voltage of the cathode. The voltage comparing circuit outputs a control signal to the first output buffer circuit in accordance with the compared result. Both of the first and second output buffer circuits are connected to a signal output terminal to be connected to a bus and a signal input terminal connected to a signal processor. The first output buffer circuit is a three state buffer circuit. While the bus driver circuit is being operated, the voltage comparing circuit compares the voltage of the cathode and the reference voltage. When the voltage of the cathode is equal to or above the reference voltage, that is, when the temperature of the first output buffer circuit becomes equal to or above the temperature Tcr, the voltage comparing circuit outputs, to the first output buffer circuit, a control signal for inactivating the first output buffer circuit. The first output buffer circuit is inactivated when the control signal is input thereto.

摘要翻译： 总线驱动器电路包括二极管，电阻器，恒压源，恒压比较电路，第一输出缓冲电路，第二输出缓冲电路。 二极管的阳极连接到电源，而其阴极连接到电阻器的一端。 电阻的另一端连接到地。 当第一输出缓冲电路的温度变为发生振铃事件的温度Tcr时，恒压源将电压比较电路施加参考电压，该参考电压与包括在二极管中的阴极的电压基本相同， 来自总线驱动电路的输出信号。 电压比较电路比较参考电压和阴极的电压。 电压比较电路根据比较结果向第一输出缓冲电路输出控制信号。 第一和第二输出缓冲器电路都连接到要连接到总线的信号输出端子和连接到信号处理器的信号输入端子。 第一输出缓冲电路是三状态缓冲电路。 当总线驱动器电路正在运行时，电压比较电路比较阴极的电压和参考电压。 当阴极的电压等于或高于参考电压时，即当第一输出缓冲电路的温度变得等于或高于温度Tcr时，电压比较电路将输出到第一输出缓冲电路 用于使第一输出缓冲电路失活的控制信号。 当输入控制信号时，第一输出缓冲电路被去激活。

公开(公告)号：US06230517B1

公开(公告)日：2001-05-15

申请号：US09351287

申请日：1999-07-12

申请人： Katsusuke Ishiguro ,  Akira Maruyama ,  Hiroshi Kamiya

发明人： Katsusuke Ishiguro ,  Akira Maruyama ,  Hiroshi Kamiya

IPC分类号： F25B1500

CPC分类号： F25B15/06 ,  F25B15/008 ,  F25B41/04 ,  Y02A30/277 ,  Y02B30/62

摘要： Lower and upper limit float switches 15a and 15b for detecting the liquid level in high-temperature separator 14, orifice portion 18 and float-associated valve V1 parallel to the orifice portion are provided, with the orifice portion being provided on circulation pipe K2 extending from the gas-liquid separator in a position either upstream or downstream of high-temperature heat exchanger 17. The float-associated valve is closed when the liquid level drops to the lower limit thereof and it is opened when the liquid level rises to the upper limit thereof. During normal operation of the cooling apparatus, the flowing of steam from the gas-liquid separator into the heat exchanging unit can be prevented to ensure smooth passage of the solution. In a diluting operation, the head of the gas-liquid separator suffices to ensure an adequate flow of the solution in spite of the small pressure difference, thereby assuring the diluting operation to proceed smoothly.

摘要翻译： 提供用于检测高温分离器14，孔部分18和平行于孔口部分的浮子关联阀V1的液位的下限和上限浮子开关15a和15b，其中孔口部分设置在循环管道K2上 气液分离器位于高温热交换器17的上游或下游的位置。当液面下降到其下限时，浮阀关闭，当液面上升到上限时打开 其中。 在冷却装置的正常操作期间，可以防止蒸气从气液分离器流入热交换单元，以确保溶液的顺利通过。 在稀释操作中，尽管压力差很小，气液分离器的头足以确保溶液的充分流动，从而确保稀释操作顺利进行。

公开(公告)号：US5698991A

公开(公告)日：1997-12-16

申请号：US607464

申请日：1996-02-27

申请人： Hiroshi Kamiya

发明人： Hiroshi Kamiya

IPC分类号： G06F3/00 ,  G06F13/40 ,  H03K5/1532 ,  H03K19/003 ,  H03K19/01 ,  H03K19/0175 ,  H04L25/02 ,  H04L25/03 ,  H03K17/16 ,  H03K19/08

CPC分类号： H04L25/028 ,  G06F13/4072 ,  H03K19/00361 ,  H04L25/03834 ,  H04L25/0292

摘要： A bus driver includes a plurality of first to m-th buffer circuits for receiving input of an input signal, a delay circuit for delaying the input signal by a predetermined time period, an n-th buffer circuit for receiving input of a delay signal from the delay circuit, a capacitor for selectively receiving input of a predetermined combination of the output signals of the first to m-th buffer circuits, and an output terminal for outputting a signal composed of the output of the capacitor and the output signal of said n-th buffer circuit. As a result of composition of a plurality of signals output from the capacitive portion and the signal output from the n-th buffer circuit, a plurality of output signals each having different rise time and fall time are output from the output terminal.

摘要翻译： 总线驱动器包括多个第一至第m缓冲电路，用于接收输入信号的输入;延迟电路，用于将输入信号延迟预定的时间段;第n个缓冲电路，用于接收来自 所述延迟电路，用于选择性地接收所述第一至第m缓冲电路的输出信号的预定组合的输入的电容器和用于输出由所述电容器的输出和所述n的输出信号组成的信号的输出端子 缓冲电路。 作为从电容部分输出的多个信号的组成和从第n个缓冲电路输出的信号的结果，从输出端子输出各自具有不同上升时间和下降时间的多个输出信号。

公开(公告)号：US5585742A

公开(公告)日：1996-12-17

申请号：US500783

申请日：1995-07-11

申请人： Hiroshi Kamiya

发明人： Hiroshi Kamiya

IPC分类号： G06F13/40 ,  H03K5/13 ,  H03K19/0175 ,  H03K19/096 ,  H03K19/003

CPC分类号： G06F13/4072

摘要： In a bus system of a computer, an enable pulse is propagated through different signal paths and bus drivers so that it takes different amounts of time to reach a common bus. Each bus driver has a tristate output buffer connected to the bus, a delay circuit and an AND gate for receiving an enable pulse from one of the signal paths. The input terminal of the delay circuit is also connected to receive the same enable pulse for introducing a predetermined amount of delay to the enable pulse and supplying the delayed pulse to the AND gate, so that the delayed pulse is truncated at the trailing edge of the enable pulse directly supplied to the AND gate. The output terminal of the AND gate is connected to the enable/disable input terminal of the tristate output buffer for enabling it with the delayed and truncated enable pulse. The amounts of delays introduced in the bus drivers are manually set so that the delayed pulses would arrive at nearly the same time at the respective output buffers if they were simultaneously transmitted.

摘要翻译： 在计算机的总线系统中，使能脉冲通过不同的信号路径和总线驱动器传播，从而达到公共总线所需的时间不同。 每个总线驱动器具有连接到总线的三态输出缓冲器，延迟电路和用于从一个信号路径接收使能脉冲的与门。 延迟电路的输入端也被连接以接收相同的使能脉冲，用于将预定量的延迟引入到使能脉冲，并将延迟的脉冲提供给与门，使得延迟的脉冲在 使能脉冲直接提供给与门。 与门的输出端连接到三态输出缓冲器的使能/禁止输入端，用于使能延迟和截止使能脉冲。 在总线驱动器中引入的延迟量被手动设置，使得如果同时发送延迟的脉冲将在相应的输出缓冲器几乎同时到达。

公开(公告)号：US5576634A

公开(公告)日：1996-11-19

申请号：US544581

申请日：1995-10-18

申请人： Hiroshi Kamiya

发明人： Hiroshi Kamiya

IPC分类号： G06F3/00 ,  H03K4/00 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0175

CPC分类号： H03K4/00 ,  H03K17/16 ,  H03K6/04

摘要： A bus driver includes differentiating and delay circuits connected together in parallel. The differentiating circuit receives an input signal via a first buffer circuit and produces a first signal having a falling and rising period. The delay circuit delays the input signal to produce a second signal output via a second buffer circuit. The second signal is delayed so that the second signal begins falling after the first signal starts falling and so that second signal begins rising after the first signal starts rising. The first and second signals are combined to produce an output signal. The preceding edge of the output signal is rounded because the relatively short falling of the first signal precedes the relatively long falling of the second signal. The following edge of the output signal is rounded because the short rising of the first signal suppresses an end portion of the long falling of the second signal. The waveform of the output signal is adjustable by changing parameters such as, for example, the delay time of the delay circuit, the capacitance of the capacitor and the power of the first and second buffer circuits.

摘要翻译： 总线驱动器包括并联连接在一起的差分和延迟电路。 微分电路通过第一缓冲电路接收输入信号，并产生具有下降和上升周期的第一信号。 延迟电路延迟输入信号以产生经由第二缓冲电路输出的第二信号。 第二信号被延迟，使得第二信号在第一信号开始下降之后开始下降，从而第二信号在第一信号开始上升之后开始上升。 第一和第二信号被组合以产生输出信号。 由于第一信号的相对短的下降在第二信号的相对长的下降之前，所以输出信号的前沿被舍入。 输出信号的下一个边缘被舍入，因为第一信号的短暂上升抑制了第二信号的长时间下降的一个端部。 通过改变诸如延迟电路的延迟时间，电容器的电容和第一和第二缓冲电路的功率的参数来调节输出信号的波形。