A pulse density modulator generates output pulses that are optimized as to their even distribution over time. More particularly, the invention represents parallel or serial digital input signals as serial binary output signals, where the binary output pulses are evenly spaced over time to the greatest extent possible. The output signal includes a pattern that repeats during successive “cycles.” The number of pulses in each cycle varies in proportion to the magnitude of the digital input signal. When a digital input signal is provided to an accumulator, the accumulator repeatedly updates a current N-bit sum value by adding the digital input signal thereto. According to this computation, the accumulator either (1) provides a first prescribed signal on a carry output if the current sum cannot be expressed in N bits, or (2) provides a different prescribed signal on the carry output if the current sum can be expressed in N bits. The carry output provides a serial binary output having 2N bits in each cycle. The accumulator may be used as a digital-to-analog converter by routing the carry output to an analog filter. Alternatively, the digital output of the accumulator may be used to provide a trigger signal of repeating, evenly spaced pulses.