A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.