公开(公告)号：US06346825B1

公开(公告)日：2002-02-12

申请号：US09680205

申请日：2000-10-06

申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： H03K19177

CPC分类号： H03K19/1776

摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.

摘要翻译： 为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。 块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。 在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。 响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。 在配置PLD期间对配置位进行编程。 在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。 在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。 在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

公开(公告)号：US07402443B1

公开(公告)日：2008-07-22

申请号：US11333819

申请日：2006-01-17

申请人： Raymond C. Pang ,  Trevor J. Bauer ,  F. Erich Goetting ,  Bruce E. Talley ,  Steven P. Young

发明人： Raymond C. Pang ,  Trevor J. Bauer ,  F. Erich Goetting ,  Bruce E. Talley ,  Steven P. Young

IPC分类号： G01R31/26

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.

摘要翻译： 提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。 第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。 第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。 第三IC管芯基本上类似于第一管芯的第一部分。 第二和第三包可以是相同的，并且包装的模具可以在系统中互换。 当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

公开(公告)号：US06282127B1

公开(公告)日：2001-08-28

申请号：US09625672

申请日：2000-07-24

申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： G11C700

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.

摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。 复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。 当RAM块被配置为状态机时，这是有用的。 因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。 当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。

公开(公告)号：US07345507B1

公开(公告)日：2008-03-18

申请号：US11333991

申请日：2006-01-17

申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

IPC分类号： H01L25/00

CPC分类号： H03K19/177

摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

摘要翻译： 多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 选择码存储电路存储产品选择码。 产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。 产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。 选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。 产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

公开(公告)号：US07491576B1

公开(公告)日：2009-02-17

申请号：US11333990

申请日：2006-01-17

申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

IPC分类号： H01L21/66 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L22/22 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

摘要翻译： 制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。 在封装之前测试IC芯片。 如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。 死亡的第二部分故意使其不能运作。 因此，IC芯片仍然可以作为全功能封装IC出售。

公开(公告)号：US07242633B1

公开(公告)日：2007-07-10

申请号：US11044740

申请日：2005-01-26

申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00

摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

公开(公告)号：US07248491B1

公开(公告)日：2007-07-24

申请号：US11044746

申请日：2005-01-26

申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/1075

摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

公开(公告)号：US06373779B1

公开(公告)日：2002-04-16

申请号：US09574300

申请日：2000-05-19

申请人： Raymond C. Pang ,  Steven P. Young

发明人： Raymond C. Pang ,  Steven P. Young

IPC分类号： G11C800

CPC分类号： H03K19/1776 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16

摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.

摘要翻译： 为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。 块RAM包括存储单元阵列和可配置为选择用于访问存储单元阵列的多个写入模式之一的控制逻辑。 在一个实施例中，写入模式包括具有回写模式的写入，不具有回写模式的写入以及读取和写入模式。 响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择写入模式。 在配置PLD期间对配置位进行编程。 在一个变化中，控制逻辑响应于用户信号选择写入模式。 在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。 在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）写入模式。 第一和第二端口的宽度也可以独立地配置。

公开(公告)号：US07515452B1

公开(公告)日：2009-04-07

申请号：US11649447

申请日：2007-01-03

申请人： Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

发明人： Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

IPC分类号： G11C11/00

CPC分类号： G11C8/04 ,  H03K19/00392 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

摘要翻译： 存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。 多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。 第二存储单元具有第三单元部分和第四单元部分。 第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。 在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。

公开(公告)号：US07157951B1

公开(公告)日：2007-01-02

申请号：US10837186

申请日：2004-04-30

申请人： Shawn K. Morrison ,  Raymond C. Pang

发明人： Shawn K. Morrison ,  Raymond C. Pang

IPC分类号： H03H11/26

CPC分类号： H03K5/15013 ,  G06F1/10

摘要： A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.

摘要翻译： 数字时钟管理器的延迟线包括抽头延迟结构和修整延迟结构。 修剪延迟结构包括第一缓冲器，其被耦合以从抽头延迟结构接收时钟信号，并且作为响应，向一组时钟线提供延迟的时钟信号。 修剪延迟结构还包括电容修剪单元，其具有从该组时钟线分离的多个电容修剪元件。 电容调整元件被选择性地使能或禁止，从而对该组时钟线上的延迟的时钟信号引入额外的延迟。 每个电容调整元件可以包括传输门结构，其被导通以将显着的结电容引入该组时钟线。 修剪延迟结构还可以包括适于缓冲该组时钟线上延迟的时钟信号的第二缓冲器。