发明授权
- 专利标题: Low latency fused multiply-adder
- 专利标题(中): 低延迟融合乘法加法器
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申请号: US09207483申请日: 1998-12-08
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公开(公告)号: US06282557B1公开(公告)日: 2001-08-28
- 发明人: Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
- 申请人: Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
- 主分类号: G06F748
- IPC分类号: G06F748
摘要:
A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
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