公开(公告)号：US07995418B2

公开(公告)日：2011-08-09

申请号：US12399551

申请日：2009-03-06

申请人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

发明人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

摘要翻译： 用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。 存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。 每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。 提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。 可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。 可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

公开(公告)号：US07551508B2

公开(公告)日：2009-06-23

申请号：US11941168

申请日：2007-11-16

申请人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

发明人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

摘要翻译： 使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。 存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。 每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。 提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。 可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。 可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

公开(公告)号：US07545690B2

公开(公告)日：2009-06-09

申请号：US11741187

申请日：2007-04-27

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50012 ,  G11C2029/1204

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。

公开(公告)号：US20080273403A1

公开(公告)日：2008-11-06

申请号：US12125011

申请日：2008-05-21

申请人： Sebastian Ehrenreich ,  Jente B. Kuang ,  Chun-Tao Li ,  Hung Cai Ngo

发明人： Sebastian Ehrenreich ,  Jente B. Kuang ,  Chun-Tao Li ,  Hung Cai Ngo

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50012

摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

摘要翻译： 包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。 存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。 访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。 测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。 多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

公开(公告)号：US06566921B1

公开(公告)日：2003-05-20

申请号：US09631718

申请日：2000-08-03

申请人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

发明人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

IPC分类号： H03L706

CPC分类号： H03L7/23

摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.

摘要翻译： 一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。 频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。 存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。 最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。 通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。 调整精度取决于分频器的相对值和系统中的中间级数。

公开(公告)号：US06393446B1

公开(公告)日：2002-05-21

申请号：US09343450

申请日：1999-06-30

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Joel Abraham Silberman

IPC分类号： G06F700

CPC分类号： G06F7/762 ,  G06F5/015

摘要： A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.

摘要翻译： 能够执行32位和64位旋转的双模旋转器。 根据优选实施例，双模旋转器包括第一，第二和第三旋转单元，其中每个旋转器具有多个输入和输出。 第二旋转器的输入可操作地连接到第一旋转单元的相应输出端。 第三旋转单元的输入可操作地连接到第二旋转器的相应输出。 响应于选择32位旋转模式，第一旋转器的输入的上半部分为零，并且第三旋转器的输出的下半部分被复制在第三旋转器的输出的上半部分中。

公开(公告)号：US06360238B1

公开(公告)日：2002-03-19

申请号：US09270469

申请日：1999-03-15

申请人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F501

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

摘要翻译： 公开了具有集成符号选择器的零/一预测器。 通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。 前导零字符串为正和，前导字符串为负数。 然后从前导零字符串和前导字符串确定归一化偏移量。 然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。 然后，利用该符号来选择正和或负的正和归一化移位量。

公开(公告)号：US06285218B1

公开(公告)日：2001-09-04

申请号：US09567381

申请日：2000-05-10

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Osamu Takahashi

IPC分类号： H03K19094

CPC分类号： H03K19/1736

摘要： A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.

摘要翻译： 用于用可编程动态逻辑门实现动态逻辑的方法和装置作为用于高速微处理器设计中的可编程逻辑阵列（PLA）的补充。 可选单元的矩阵提供强大的逻辑功能，例如具有最小输入和晶体管的AND-OR门能力。 通过使用可编程逻辑阵列和可编程动态门，逻辑块的效率可以大大提高，几乎没有增加电路面积。

公开(公告)号：US09274751B2

公开(公告)日：2016-03-01

申请号：US11776454

申请日：2007-07-11

申请人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

发明人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

IPC分类号： G06F7/533 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US09076509B2

公开(公告)日：2015-07-07

申请号：US12511666

申请日：2009-07-29

申请人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。