发明授权
- 专利标题: Method to reduce compressive stress in the silicon substrate during silicidation
- 专利标题(中): 降低硅衬底中压缩应力的方法
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申请号: US09666315申请日: 2000-09-21
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公开(公告)号: US06284610B1公开(公告)日: 2001-09-04
- 发明人: Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
- 申请人: Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
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