公开(公告)号：US07573081B2

公开(公告)日：2009-08-11

申请号：US11519103

申请日：2006-09-11

申请人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L29/78

CPC分类号： H01L21/76834 ,  H01F3/14 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F41/045 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

摘要翻译： 提供了一种在硅衬底的表面上形成电感器的新方法。 本发明提供金属电感器下面的氧化物鳍片的覆盖层。 氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。 通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。 衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

公开(公告)号：US07105420B1

公开(公告)日：2006-09-12

申请号：US09413177

申请日：1999-10-07

申请人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L21/76

CPC分类号： H01L21/76834 ,  H01F3/14 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F41/045 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

公开(公告)号：US20070007623A1

公开(公告)日：2007-01-11

申请号：US11519103

申请日：2006-09-11

申请人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L29/00

CPC分类号： H01L21/76834 ,  H01F3/14 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F41/045 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

摘要翻译： 提供了一种在硅衬底的表面上形成电感器的新方法。 本发明提供金属电感器下面的氧化物鳍片的覆盖层。 氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。 通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。 衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

公开(公告)号：US06348385B1

公开(公告)日：2002-02-19

申请号：US09726256

申请日：2000-11-30

申请人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

发明人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/7834

摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

摘要翻译： 使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。 在基板上形成虚拟栅极。 使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。 在源极和漏极区上的衬底上形成掩模层。 我们删除虚拟门。 在掩蔽层的侧壁上形成掺杂的低k间隔物。 掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。 我们在掩模层上形成一个高k栅介质层。 在高K电介质层上形成栅极层。 栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

公开(公告)号：US06221727B1

公开(公告)日：2001-04-24

申请号：US09385524

申请日：1999-08-30

申请人： Lap Chan ,  Johnny Kok Wai Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Johnny Kok Wai Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01L21/764 ,  H01L27/08

摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.

摘要翻译： 描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。 在半导体衬底中形成场氧化物区域，然后去除，从而在半导体衬底中留下阱。 抛光停止层沉积在基底上并在孔内。 抛光停止层被覆盖并充满了旋涂玻璃层。 旋涂玻璃层被抛光回抛光停止层。 所述抛光停止层被去除。 沉积在旋涂玻璃层和半导体衬底上的第一氧化物层，并且使用电感器掩模版进行图案化，由此通过第一氧化物层到旋涂玻璃层制成多个开口。 孔内的所有旋涂玻璃层通过多个开口被去除。 此后，将第二氧化物层沉积在第一氧化物层上并覆盖多个开口，从而在该阱内形成空气屏障。 沉积在第二氧化物层上的金属层，并使用相同的电感器掩模版进行图案化以在集成电路器件的制造中形成电感器。

公开(公告)号：US6140197A

公开(公告)日：2000-10-31

申请号：US385525

申请日：1999-08-30

申请人： Shau-Fu Sanford Chu ,  Kok Wai Johnny Chew ,  Chee Tee Chua ,  Cher Liang Cha

发明人： Shau-Fu Sanford Chu ,  Kok Wai Johnny Chew ,  Chee Tee Chua ,  Cher Liang Cha

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L21/20

CPC分类号： H01L28/10 ,  H01L27/08

摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the dielectric layer. The intermetal dielectric layer is patterned whereby a plurality of openings are made through the intermetal dielectric layer to the semiconductor substrate. Thereafter, an oxide layer is deposited overlying the intermetal dielectric layer and capping the plurality of openings thereby forming air gaps within the intermetal dielectric layer. A metal plug is formed through the oxide layer and the intermetal dielectric layer to the metal line. A metal layer is deposited overlying the oxide layer and patterned to form an inductor wherein a portion of the inductor contacts the metal line through the metal plug to complete formation of an inductor utilizing air as an underlying barrier in the fabrication of an integrated circuit.

摘要翻译： 描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。 提供了覆盖半导体衬底上的电介质层的金属线。 覆盖在金属线和电介质层上的金属间电介质层。 金属间电介质层被图案化，由此通过金属间电介质层制造多个开口到半导体衬底。 此后，将氧化物层沉积在金属间电介质层上并覆盖多个开口，从而在金属间电介质层内形成气隙。 通过氧化物层和金属间电介质层形成金属插塞到金属线。 将金属层沉积在氧化物层上并被图案化以形成电感器，其中电感器的一部分通过金属插塞接触金属线，以在集成电路的制造中利用空气作为潜在的阻挡层来形成电感器。

公开(公告)号：US06284610B1

公开(公告)日：2001-09-04

申请号：US09666315

申请日：2000-09-21

申请人： Randall Cher Liang Cha ,  Chee Tee Chua ,  Kin Leong Pey ,  Lap Chan

发明人： Randall Cher Liang Cha ,  Chee Tee Chua ,  Kin Leong Pey ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/7845

摘要： A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.

摘要翻译： 描述了用于硅化源极/漏极结的方法，其中通过在硅化物和硅之间插入缓冲层来避免下面的硅的压缩应力。 栅极电极和相关的源极/漏极延伸部设置在半导体衬底中和半导体衬底上。 沉积在半导体衬底和栅电极上的缓冲氧化层。 堆叠在缓冲氧化物层上的多晶硅层。 多晶硅层将形成源极/漏极结和硅源。 源极/漏极结是硅化的，由此缓冲氧化物层在硅化期间提供压缩应力释放。

公开(公告)号：US6121130A

公开(公告)日：2000-09-19

申请号：US192338

申请日：1998-11-16

申请人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

发明人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

IPC分类号： H01L21/268 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/469

CPC分类号： H01L21/76825 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/268 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76834

摘要： A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm.sup.2. Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.

摘要翻译： 描述了通过激光扫描固化基于烷基倍半硅氧烷聚合物的低k自旋电介质层的方法，其中通过光热和光化学机理实现固化。 通过旋转沉积沉积这些层，通过用0.1至1焦耳/ cm2的能量的脉冲激光进行光栅扫描来干燥和固化。 因为激光引起层的加热，所以在扫描激光束之后施加氮气喷射以快速冷却层并抑制氧化和吸湿。 激光诱导加热还有助于排出水分和聚合过程的副产物。 激光器工作在200和400 nm之间的波长。 绝缘层例如氧化硅在这些处是足够透明的，使得覆盖聚合物层的氧化物段不会阻碍固化过程。 激光扫描特征的实现容易地并入现有的旋涂沉积和固化工具中。