发明授权
- 专利标题: Method of reducing RIE lag for deep trench silicon etching
- 专利标题(中): 减少深沟槽硅蚀刻RIE滞后的方法
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申请号: US09583963申请日: 2000-05-31
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公开(公告)号: US06284666B1公开(公告)日: 2001-09-04
- 发明人: Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
- 申请人: Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
- 主分类号: H01L21302
- IPC分类号: H01L21302
摘要:
A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,
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