发明授权
US06284666B1 Method of reducing RIE lag for deep trench silicon etching 失效
减少深沟槽硅蚀刻RIE滞后的方法

Method of reducing RIE lag for deep trench silicon etching
摘要:
A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,
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